公开(公告)号：US20130134491A1

公开(公告)日：2013-05-30

申请号：US13307874

申请日：2011-11-30

申请人： Brian W. Messenger ,  Paul C. Parries ,  Chengwen Pei ,  Geng Wang ,  Yanli Zhang

发明人： Brian W. Messenger ,  Paul C. Parries ,  Chengwen Pei ,  Geng Wang ,  Yanli Zhang

IPC分类号： H01L27/108 ,  H01L21/02

CPC分类号： H01L27/10829 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/481 ,  H01L27/1087 ,  H01L27/1203 ,  H01L29/66181 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a trench structure that includes forming a metal containing layer on at least the sidewalls of a trench, and forming an undoped semiconductor fill material within the trench. The undoped semiconductor fill material and the metal containing layer are recessed to a first depth within the trench with a first etch. The undoped semiconductor fill material is then recessed to a second depth within the trench that is greater than a first depth with a second etch. The second etch exposes at least a sidewall portion of the metal containing layer. The trench is filled with a doped semiconductor containing material fill, wherein the doped semiconductor material fill is in direct contact with the at least the sidewall portion of the metal containing layer.

摘要翻译： 一种形成沟槽结构的方法，其包括在至少沟槽的侧壁上形成含金属层，以及在所述沟槽内形成未掺杂的半导体填充材料。 未掺杂的半导体填充材料和含金属层通过第一蚀刻凹陷到沟槽内的第一深度。 然后将未掺杂的半导体填充材料凹入到沟槽内的第二深度，其大于具有第二蚀刻的第一深度。 第二蚀刻暴露了含金属层的至少一个侧壁部分。 沟槽填充有掺杂的半导体含有材料填充物，其中掺杂半导体材料填充物与含金属层的至少侧壁部分直接接触。

公开(公告)号：US20130009277A1

公开(公告)日：2013-01-10

申请号：US13617576

申请日：2012-09-14

申请人： Abhishek Dube ,  Subramanian S. Iyer ,  Babar Ali Khan ,  Oh-jung Kwon ,  Junedong Lee ,  Paul C. Parries ,  Chengwen Pei ,  Gerd Pfeiffer ,  Ravi M. Todi ,  Geng Wang

发明人： Abhishek Dube ,  Subramanian S. Iyer ,  Babar Ali Khan ,  Oh-jung Kwon ,  Junedong Lee ,  Paul C. Parries ,  Chengwen Pei ,  Gerd Pfeiffer ,  Ravi M. Todi ,  Geng Wang

IPC分类号： H01L29/06

CPC分类号： H01L29/945 ,  H01L21/76229 ,  H01L21/84 ,  H01L29/66181

摘要： A structure and method for forming isolation and a buried plate for a trench capacitor is disclosed. Embodiments of the structure comprise an epitaxial layer serving as the buried plate, and a bounded deep trench isolation area serving to isolate one or more deep trench structures. Embodiments of the method comprise angular implanting of the deep trench isolation area to form a P region at the base of the deep trench isolation area that serves as an anti-punch through implant.

摘要翻译： 公开了用于形成隔离的结构和方法以及用于沟槽电容器的掩埋板。 该结构的实施例包括用作掩埋板的外延层和用于隔离一个或多个深沟槽结构的有界深沟槽隔离区域。 该方法的实施例包括深沟槽隔离区域的角度注入，以在用作抗穿孔植入物的深沟槽隔离区域的底部形成P区。

公开(公告)号：US08298884B2

公开(公告)日：2012-10-30

申请号：US12862048

申请日：2010-08-24

申请人： Geng Wang ,  Joseph Ervin ,  Jeffrey B. Johnson ,  Paul C. Parries

发明人： Geng Wang ,  Joseph Ervin ,  Jeffrey B. Johnson ,  Paul C. Parries

IPC分类号： H01L21/338

CPC分类号： H01L29/66772 ,  H01L21/2652 ,  H01L29/78696

摘要： The present disclosure provides a semiconductor device that may include a substrate including a semiconductor layer overlying an insulating layer. A gate structure that is present on a channel portion of the semiconductor layer. A first dopant region is present in the channel portion of the semiconductor layer, in which the peak concentration of the first dopant region is present within the lower portion of the gate conductor and the upper portion of the semiconductor layer. A second dopant region is present in the channel portion of the semiconductor layer, in which the peak concentration of the second dopant region is present within the lower portion of the semiconductor layer.

摘要翻译： 本公开提供了一种半导体器件，其可以包括包括覆盖绝缘层的半导体层的衬底。 存在于半导体层的沟道部分上的栅极结构。 第一掺杂区存在于半导体层的沟道部分中，其中第一掺杂区的峰值浓度存在于栅极导体的下部和半导体层的上部之间。 第二掺杂剂区域存在于半导体层的沟道部分中，其中第二掺杂剂区域的峰值浓度存在于半导体层的下部。

公开(公告)号：US08273629B2

公开(公告)日：2012-09-25

申请号：US12701972

申请日：2010-02-08

申请人： Geng Wang ,  Paul C. Parries

发明人： Geng Wang ,  Paul C. Parries

IPC分类号： H01L21/336

CPC分类号： H01L21/84 ,  H01L29/105 ,  H01L29/66537 ,  H01L29/6656 ,  H01L29/66772

摘要： The present invention, provides a semiconductor device including a substrate including a semiconductor layer overlying an insulating layer, wherein a back gate structure is present underlying the insulating layer and a front gate structure on the semiconductor layer; a channel dopant region underlying the front gate structure of the substrate, wherein the channel dopant region has a first concentration present at an interface of the semiconductor layer and the insulating layer and at least a second concentration present at the interface of the front gate structure and the semiconductor layer, wherein the first concentration is greater than the second concentration; and a source region and drain region present in the semiconductor layer of the substrate.

摘要翻译： 本发明提供一种半导体器件，其包括：衬底，其包括覆盖绝缘层的半导体层，其中在所述绝缘层下面存在背栅结构，并且在所述半导体层上存在前栅极结构; 在衬底的前栅极结构下面的沟道掺杂剂区域，其中沟道掺杂剂区域具有存在于半导体层和绝缘层的界面处的第一浓度，以及存在于前栅极结构的界面处的至少第二浓度和 所述半导体层，其中所述第一浓度大于所述第二浓度; 以及存在于衬底的半导体层中的源极区和漏极区。

公开(公告)号：US20120049295A1

公开(公告)日：2012-03-01

申请号：US12862048

申请日：2010-08-24

申请人： Geng Wang ,  Joseph Ervin ,  Jeffrey B. Johnson ,  Paul C. Parries

发明人： Geng Wang ,  Joseph Ervin ,  Jeffrey B. Johnson ,  Paul C. Parries

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66772 ,  H01L21/2652 ,  H01L29/78696

摘要： The present disclosure provides a semiconductor device that may include a substrate including a semiconductor layer overlying an insulating layer. A gate structure that is present on a channel portion of the semiconductor layer. A first dopant region is present in the channel portion of the semiconductor layer, in which the peak concentration of the first dopant region is present within the lower portion of the gate conductor and the upper portion of the semiconductor layer. A second dopant region is present in the channel portion of the semiconductor layer, in which the peak concentration of the second dopant region is present within the lower portion of the semiconductor layer.

公开(公告)号：US07888723B2

公开(公告)日：2011-02-15

申请号：US12016312

申请日：2008-01-18

申请人： MaryJane Brodsky ,  Kangguo Cheng ,  Herbert L. Ho ,  Paul C. Parries ,  Kevin R. Winstel

发明人： MaryJane Brodsky ,  Kangguo Cheng ,  Herbert L. Ho ,  Paul C. Parries ,  Kevin R. Winstel

IPC分类号： H01L29/94

CPC分类号： H01L29/66181 ,  H01L21/84 ,  H01L27/1087

摘要： A deep trench is formed to a depth midway into a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A top semiconductor layer is laterally recessed by an isotropic etch that is selective to the buried insulator layer. The deep trench is then etched below a bottom surface of the buried insulator layer. Ion implantation is performed at an angle into the deep trench to dope the sidewalls of the deep trench beneath the buried insulator layer, while the laterally recessed sidewalls of the top semiconductor layer are not implanted with dopant ions. A node dielectric and trench fill materials are deposited into the deep trench. A buried strap has an upper buried strap sidewall that is offset from a lower buried strap sidewall and a deep trench sidewall.

摘要翻译： 深沟槽形成在绝缘体上半导体（SOI）衬底的埋入绝缘体层的中间的深度处。 顶部半导体层通过对掩埋绝缘体层有选择性的各向同性蚀刻而横向凹陷。 然后将深沟槽蚀刻在掩埋绝缘体层的底表面下方。 离子注入以一定角度进入深沟槽以掺杂隐埋绝缘体层下面的深沟槽的侧壁，而顶部半导体层的侧向凹入的侧壁不注入掺杂离子。 节点电介质和沟槽填充材料沉积到深沟槽中。 掩埋带具有从下埋置带侧壁和深沟槽侧壁偏移的上掩埋带侧壁。

公开(公告)号：US20100237417A1

公开(公告)日：2010-09-23

申请号：US12701972

申请日：2010-02-08

申请人： Geng Wang ,  Paul C. Parries

发明人： Geng Wang ,  Paul C. Parries

IPC分类号： H01L27/12 ,  H01L21/86

CPC分类号： H01L21/84 ,  H01L29/105 ,  H01L29/66537 ,  H01L29/6656 ,  H01L29/66772

摘要： The present invention, provides a semiconductor device including a substrate including a semiconductor layer overlying an insulating layer, wherein a back gate structure is present underlying the insulating layer and a front gate structure on the semiconductor layer; a channel dopant region underlying the front gate structure of the substrate, wherein the channel dopant region has a first concentration present at an interface of the semiconductor layer and the insulating layer and at least a second concentration present at the interface of the front gate structure and the semiconductor layer, wherein the first concentration is greater than the second concentration; and a source region and drain region present in the semiconductor layer of the substrate.

摘要翻译： 本发明提供一种半导体器件，其包括：衬底，其包括覆盖绝缘层的半导体层，其中在所述绝缘层下面存在背栅结构，并且在所述半导体层上存在前栅极结构; 在衬底的前栅极结构下面的沟道掺杂剂区域，其中沟道掺杂剂区域具有存在于半导体层和绝缘层的界面处的第一浓度，以及存在于前栅极结构的界面处的至少第二浓度和 所述半导体层，其中所述第一浓度大于所述第二浓度; 以及存在于衬底的半导体层中的源极区和漏极区。

公开(公告)号：US07078756B2

公开(公告)日：2006-07-18

申请号：US10904933

申请日：2004-12-06

申请人： Yoichi Otani ,  Herbert L. Ho ,  Babar A. Khan ,  Paul C. Parries

发明人： Yoichi Otani ,  Herbert L. Ho ,  Babar A. Khan ,  Paul C. Parries

IPC分类号： H01L27/108

CPC分类号： H01L29/945 ,  H01L27/1087

摘要： The present invention provides collarless trench semiconductor memory devices having minimized vertical parasitic FET leakage and methods of forming the same.

摘要翻译： 本发明提供了具有最小的垂直寄生FET泄漏的无凹槽沟槽半导体存储器件及其形成方法。

公开(公告)号：US4873205A

公开(公告)日：1989-10-10

申请号：US240421

申请日：1988-09-01

申请人： Dale L. Critchlow ,  John K. DeBrosse ,  Rick L. Mohler ,  Wendell P. Noble, Jr. ,  Paul C. Parries

发明人： Dale L. Critchlow ,  John K. DeBrosse ,  Rick L. Mohler ,  Wendell P. Noble, Jr. ,  Paul C. Parries

IPC分类号： H01L21/74 ,  H01L21/8242

CPC分类号： H01L27/10861 ,  H01L21/743 ,  Y10S148/025 ,  Y10S148/026

摘要： A method for forming a silicide bridge bewteen a diffusion region and an adjacent poly-filled trench separated by a thin dielectric. Silicon is selectively grown over exposed silicon regions under conditions that provide controlled lateral growth over the thin dielectric without also permitting lateral growth over other insulator regions. A refractory metal layer is then deposited and sintered under conditions that limit lateral silicide growth, forming the bridge. This process avoids the random fails produced by previous processes while enhancing the compatibility of bridge formation with shallow junctions, without introducing extra masking steps or other process complexities.

摘要翻译： 用于形成硅化物桥的方法是由薄电介质隔开的扩散区和相邻的多晶填充沟槽。 硅在暴露的硅区域选择性地生长，条件是在薄介电层上提供受控的横向生长，而不允许在其它绝缘体区域上的横向生长。 然后在限制侧向硅化物生长的条件下沉积和烧结难熔金属层，形成桥。 该过程避免了以前的过程产生的随机失败，同时增强了与浅结的桥形成的兼容性，而不引入额外的掩蔽步骤或其他过程复杂性。