公开(公告)号：US08195855B2

公开(公告)日：2012-06-05

申请号：US12477545

申请日：2009-06-03

申请人： Deog-Kyoon Jeong ,  Suhwan Kim ,  Woo-Yeol Shin ,  Dong-Hyuk Lim ,  Ic-Su Oh

发明人： Deog-Kyoon Jeong ,  Suhwan Kim ,  Woo-Yeol Shin ,  Dong-Hyuk Lim ,  Ic-Su Oh

IPC分类号： G06F13/00 ,  G05F3/16 ,  H03K17/16

CPC分类号： G06F13/4086

摘要： A bus system includes a plurality of stubs; a plurality of connectors, each of which is serially coupled between a corresponding one of the stubs and a corresponding one of memory modules; a plurality of first serial loads, each of which is serially coupled to a corresponding one of the connectors; and a plurality of second serial loads, each of which is serially coupled to characteristic impedance of a transmission line of a corresponding one of the stubs, wherein the first and the second serial loads are determined to be impedance matched at each transmission line terminal of the stubs.

摘要翻译： 总线系统包括多个短截线; 多个连接器，每个连接器串联耦合在相应的一个短截线和相应的一个存储器模块之间; 多个第一串联负载，每个第一串联负载串联耦合到对应的一个连接器; 以及多个第二串联负载，每个第二串联负载串联耦合到相应一个短截线的传输线的特征阻抗，其中第一和第二串联负载被确定为在 存根

公开(公告)号：US07903684B2

公开(公告)日：2011-03-08

申请号：US11828286

申请日：2007-07-25

申请人： Dongyun Lee ,  Yeshik Shin ,  David D. Lee ,  Deog-Kyoon Jeong ,  Shing Kong

发明人： Dongyun Lee ,  Yeshik Shin ,  David D. Lee ,  Deog-Kyoon Jeong ,  Shing Kong

IPC分类号： H04J3/00 ,  G06F13/00

CPC分类号： H04L47/10 ,  H04L47/245 ,  H04L47/34 ,  H04L47/365

摘要： A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network, such as a storage area network. The Storage Link architecture specifies various communications techniques that can be combined to reduce the overall cost and increase the overall performance of communications. The Storage Link architecture may provide packet ordering based on packet type, dynamic segmentation of packets, asymmetric packet ordering, packet nesting, variable-sized packet headers, and use of out-of-band symbols to transmit control information as described below in more detail. The Storage Link architecture may also specify encoding techniques to optimize transitions and to ensure DC-balance.

摘要翻译： 用于在主机和数据存储设备之间通信的串行通信架构。 Storage Link架构特别适用于通过交换网络（如存储区域网络）支持多个主机和存储设备之间的通信。 存储链路架构规定了可以组合的各种通信技术，以降低总体成本并提高通信的整体性能。 存储链路架构可以基于分组类型，分组的动态分段，不对称分组排序，分组嵌套，可变大小的分组报头以及使用带外符号来发送控制信息来提供分组排序，如以下更详细地描述的 。 存储链路架构还可以指定编码技术来优化转换并确保直流平衡。

公开(公告)号：US07746798B2

公开(公告)日：2010-06-29

申请号：US10045625

申请日：2001-11-07

申请人： Yeshik Shin ,  David D. Lee ,  Deog-Kyoon Jeong ,  Shing Kong

发明人： Yeshik Shin ,  David D. Lee ,  Deog-Kyoon Jeong ,  Shing Kong

IPC分类号： H04L12/18

CPC分类号： H04L47/10 ,  H04L47/245 ,  H04L47/34 ,  H04L47/365

摘要： A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network, such as a storage area network. The Storage Link architecture specifies various communications techniques that can be combined to reduce the overall cost and increase the overall performance of communications. The Storage Link architecture may provide packet ordering based on packet type, dynamic segmentation of packets, asymmetric packet ordering, packet nesting, variable-sized packet headers, and use of out-of-band symbols to transmit control information as described below in more detail. The Storage Link architecture may also specify encoding techniques to optimize transitions and to ensure DC-balance.

摘要翻译： 用于在主机和数据存储设备之间通信的串行通信架构。 Storage Link架构特别适用于通过交换网络（如存储区域网络）支持多个主机和存储设备之间的通信。 存储链路架构规定了可以组合的各种通信技术，以降低总体成本并提高通信的整体性能。 存储链路架构可以基于分组类型，分组的动态分段，不对称分组排序，分组嵌套，可变大小的分组报头以及使用带外符号来发送控制信息来提供分组排序，如以下更详细地描述的 。 存储链路架构还可以指定编码技术来优化转换并确保直流平衡。

公开(公告)号：US07495590B2

公开(公告)日：2009-02-24

申请号：US11926503

申请日：2007-10-29

申请人： Deog-Kyoon Jeong ,  Won-Jun Choe

发明人： Deog-Kyoon Jeong ,  Won-Jun Choe

IPC分类号： H03M1/06

CPC分类号： H03M1/1019 ,  G09G3/3685 ,  G09G2310/027 ,  G09G2320/0209 ,  G09G2330/026 ,  H03M1/662

摘要： A technique for removing vertical stripe artifacts generated in a Liquid Crystal Display (LCD) panel, more particularly a technique for compensating for and removing an inter-channel offset voltage of a column driver, which causes the vertical stripe artifacts, is disclosed. An offset voltage generated in each channel for driving each pixel of the LCD panel is detected for a whole signal path and offset voltages detected for all channels are compared and extracted according to a given timing sequence by a common signal comparator, thereby preventing the offset of the detection comparator and reducing a chip size of the column driver in contrary to the prior art. Moreover, an inter-channel offset voltage is detected in a digital circuit mode, thereby compensating for process variations in a semiconductor chip manufacturing process in circuit terms.

摘要翻译： 公开了一种用于去除在液晶显示器（LCD）面板中产生的垂直条纹伪像的技术，更具体地说，一种用于补偿和去除导致垂直条纹伪影的列驱动器的通道间偏移电压的技术。 针对整个信号路径检测用于驱动LCD面板的每个像素的每个通道中产生的偏移电压，并且通过公共信号比较器根据给定的定时序列来对所有通道检测到的偏移电压进行比较和提取，从而防止 检测比较器并且与现有技术相反地减小列驱动器的芯片尺寸。 此外，以数字电路模式检测信道间偏移电压，从而以电路方式补偿半导体芯片制造工艺中的工艺变化。

公开(公告)号：US07340558B2

公开(公告)日：2008-03-04

申请号：US10045601

申请日：2001-11-07

申请人： Dongyun Lee ,  Yeshik Shin ,  David D. Lee ,  Deog-Kyoon Jeong ,  Shing Kong

发明人： Dongyun Lee ,  Yeshik Shin ,  David D. Lee ,  Deog-Kyoon Jeong ,  Shing Kong

IPC分类号： G06F12/06 ,  G06F13/00 ,  G06F3/00 ,  G11C29/00 ,  G11C7/10 ,  G11C8/00

CPC分类号： H04L47/10 ,  H04L47/245 ,  H04L47/34 ,  H04L47/365

摘要： A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network, such as a storage area network. The Storage Link architecture specifies various communications techniques that can be combined to reduce the overall cost and increase the overall performance of communications. The Storage Link architecture may provide packet ordering based on packet type, dynamic segmentation of packets, asymmetric packet ordering, packet nesting, variable-sized packet headers, and use of out-of-band symbols to transmit control information as described below in more detail. The Storage Link architecture may also specify encoding techniques to optimize transitions and to ensure DC-balance.

摘要翻译： 用于在主机和数据存储设备之间通信的串行通信架构。 Storage Link架构特别适用于通过交换网络（如存储区域网络）支持多个主机和存储设备之间的通信。 存储链路架构规定了可以组合的各种通信技术，以降低总体成本并提高通信的整体性能。 存储链路架构可以基于分组类型，分组的动态分段，不对称分组排序，分组嵌套，可变大小的分组报头以及使用带外符号来发送控制信息来提供分组排序，如以下更详细地描述的 。 存储链路架构还可以指定编码技术来优化转换并确保直流平衡。

公开(公告)号：US06888417B2

公开(公告)日：2005-05-03

申请号：US10613442

申请日：2003-07-03

申请人： Yongsam Moon ,  Gijung Ahn ,  Deog-Kyoon Jeong

发明人： Yongsam Moon ,  Gijung Ahn ,  Deog-Kyoon Jeong

IPC分类号： H03L7/091 ,  H03L7/113 ,  H03L7/14 ,  H04L7/033 ,  H04L7/04 ,  H03B5/00 ,  H03F3/45

CPC分类号： H04L7/033 ,  H03L7/091 ,  H03L7/113 ,  H03L7/14 ,  H04L7/04 ,  Y10S331/02

摘要： A folded starved inverter differential output apparatus for use in a voltage controlled oscillator includes a first polarity of two transistors that are cross-coupled and a second polarity of four transistors. Also included are two inverter gates and a supply regulator.

摘要翻译： 用于压控振荡器的折叠的饥饿型逆变器差分输出装置包括交叉耦合的两个晶体管的第一极性和四个晶体管的第二极性。 还包括两个逆变器门和电源调节器。

公开(公告)号：US06771192B1

公开(公告)日：2004-08-03

申请号：US10045600

申请日：2001-11-07

申请人： Dongyun Lee ,  Yeshik Shin ,  David D. Lee ,  Deog-Kyoon Jeong ,  Shing Kong

发明人： Dongyun Lee ,  Yeshik Shin ,  David D. Lee ,  Deog-Kyoon Jeong ,  Shing Kong

IPC分类号： H03M500

CPC分类号： H04L47/10 ,  H04L47/245 ,  H04L47/34 ,  H04L47/365

摘要： A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network, such as a storage area network. The Storage Link architecture specifies various communications techniques that can be combined to reduce the overall cost and increase the overall performance of communications. The Storage Link architecture may provide packet ordering based on packet type, dynamic segmentation of packets, asymmetric packet ordering, packet nesting, variable-sized packet headers, and use of out-of-band symbols to transmit control information as described below in more detail. The Storage Link architecture may also specify encoding techniques to optimize transitions and to ensure DC-balance.

摘要翻译： 用于在主机和数据存储设备之间通信的串行通信架构。 Storage Link架构特别适用于通过交换网络（如存储区域网络）支持多个主机和存储设备之间的通信。 存储链路架构规定了可以组合的各种通信技术，以降低总体成本并提高通信的整体性能。 存储链路架构可以基于分组类型，分组的动态分段，不对称分组排序，分组嵌套，可变大小的分组报头以及使用带外符号来发送控制信息来提供分组排序，如以下更详细地描述的 。 存储链路架构还可以指定编码技术来优化转换并确保直流平衡。

公开(公告)号：US06756828B2

公开(公告)日：2004-06-29

申请号：US10196479

申请日：2002-07-17

申请人： Kyeongho Lee ,  Deog-Kyoon Jeong

发明人： Kyeongho Lee ,  Deog-Kyoon Jeong

IPC分类号： H03L706

CPC分类号： H04B1/403 ,  H03F2200/372 ,  H03H11/22 ,  H03H2011/0494 ,  H03K9/00 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/0996 ,  H03L7/1974 ,  H04B1/28 ,  H04B1/40

摘要： A phase lock loop (PLL) and methods for using same is provided that includes a multiple-feedback CMOS voltage control oscillator (VCO) and multi-phase sampling fractional-N prescaler. The PLL provides increased performance characteristics for a single chip CMOS radio frequency (RF) communications system. The multiple feedback CMOS VCO maintains an amplitude of a VCO signal while reducing a rise/fall time of the VCO signal. The multiple feedback CMOS VCO further reduces supply noise effects. The multi-phase sampling fractional-N prescaler provides sufficient bandwidth for a CMOS VCO while maintaining spectral purity and reducing fractional-spur. The multi-phase sampling fractional-N prescaler can include a divider, a sampler circuit, a selector circuit and a modular counter.

摘要翻译： 提供了一种锁相环（PLL）及其使用方法，包括多反馈CMOS压控振荡器（VCO）和多相采样分数N预分频器。 PLL为单芯片CMOS射频（RF）通信系统提供了更高的性能特性。 多反馈CMOS VCO在降低VCO信号的上升/下降时间的同时保持VCO信号的幅度。 多反馈CMOS VCO进一步降低了电源噪声影响。 多相采样分数N预分频器为CMOS VCO提供足够的带宽，同时保持光谱纯度并减少分数。 多相采样分数N预分频器可以包括分频器，采样器电路，选择器电路和模块化计数器。

公开(公告)号：US06538498B2

公开(公告)日：2003-03-25

申请号：US10113600

申请日：2002-04-02

申请人： Kyeongho Lee ,  Deog-Kyoon Jeong

发明人： Kyeongho Lee ,  Deog-Kyoon Jeong

IPC分类号： H03K500

CPC分类号： H04B1/28 ,  H03F2200/372 ,  H03H11/22 ,  H03H2011/0494 ,  H03K9/00 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/1974 ,  H04B1/40 ,  H04B1/403

摘要： A tuning circuit for an RF communications system and method includes a master block that outputs a control signal to a slave block. The master block can include a first filter having a high pass filter and a low pass filter that each receive the control signal, a first rectifier coupled to the high pass filter, a second rectifier coupled to the low pass filter, and a converter coupled to the first and second rectifiers that outputs the control signal. The first filter is preferably a gm-C poly-phase filter. Output signals of the gm-C poly-phase filter include high and low pass filtering signals resulting from similarly configured circuits so that the output signals have the same electrical characteristics, which results in an increased accuracy, for example, in a cut-off frequency.

公开(公告)号：US06510185B2

公开(公告)日：2003-01-21

申请号：US09897975

申请日：2001-07-05

申请人： Kyeongho Lee ,  Deog-Kyoon Jeong

发明人： Kyeongho Lee ,  Deog-Kyoon Jeong

IPC分类号： H03D324

CPC分类号： H03H11/22 ,  H03D7/1441 ,  H03H2011/0494 ,  H03K9/00 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/1974 ,  H04B1/403

摘要： A single chip RF communication system and method is provided including a transmitter and a receiver. The RF communication system in accordance with the present invention includes an antenna for receiving transmitting RF signals, a PLL for generating multi-phase clock signals having a frequency different from a carrier frequency in response to the multi-phase clock signals and a reference signal having the carrier frequency, a demodulation-mixing unit for mixing the received RF signals with the multi-phase clock signals having the frequency different from the carrier frequency to output the RF signals having a frequency reduced by the carrier frequency and an A/D converting unit for converting the RF signals from the mixing unit into digital signals.