利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

81 条记录 (耗时 0.018 秒)

    Tracked 3X oversampling receiver
    2.
    发明授权
    Tracked 3X oversampling receiver 有权
    追踪3X过采样接收器

    公开(公告)号：US07203260B2

    公开(公告)日：2007-04-10

    申请号：US10612840

    申请日：2003-07-03

    申请人： Yongsam Moon ,  Gijung Ahn ,  Deog-Kyoon Jeong

    发明人： Yongsam Moon ,  Gijung Ahn ,  Deog-Kyoon Jeong

    IPC分类号： H04L7/00 ,  H03L7/095 ,  H03D3/24

    CPC分类号： H04L7/033 ,  H03L7/091 ,  H03L7/113 ,  H03L7/14 ,  H04L7/04 ,  Y10S331/02

    摘要： A method of receiving data, in accordance with an embodiment of the present invention, includes the acts of generating a data sampling clock signal and comparing a received clock signal to the data sampling clock signal. The data sampling clock signal is used to sample a data signal into sampled data representing a first zone, a second zone, and a third zone of the data signal. It is then determined which zone of the sampled data has a transition of the data signal and indicating a direction of change for the data sampling clock signal if the first zone or the third zone has the transition.

    摘要翻译： 根据本发明实施例的接收数据的方法包括产生数据采样时钟信号并将接收的时钟信号与数据采样时钟信号进行比较的动作。 数据采样时钟信号用于将数据信号采样成表示数据信号的第一区，第二区和第三区的采样数据。 如果第一区域或第三区域具有转变，则确定采样数据的哪个区域具有数据信号的转变并且指示数据采样时钟信号的改变方向。

    Wide range multi-phase delay-locked loop
    3.
    发明授权
    Wide range multi-phase delay-locked loop 有权
    宽范围多相延时锁定环路

    公开(公告)号：US06876240B2

    公开(公告)日：2005-04-05

    申请号：US10722842

    申请日：2003-11-25

    申请人： Yongsam Moon ,  Gijung Ahn ,  Deog-Kyoon Jeong

    发明人： Yongsam Moon ,  Gijung Ahn ,  Deog-Kyoon Jeong

    IPC分类号： H03L7/091 ,  H03L7/113 ,  H03L7/14 ,  H04L7/033 ,  H04L7/04 ,  H03L7/06

    CPC分类号： H04L7/033 ,  H03L7/091 ,  H03L7/113 ,  H03L7/14 ,  H04L7/04 ,  Y10S331/02

    摘要： A delay locked loop apparatus includes a first delay element to receive a reference signal, to delay the reference signal by a delay time, and to output a first delayed signal. A second delay element is used to receive the first delayed signal, to delay the first signal delayed signal by the delay time, and to output a second delayed signal. Also included is a harmonic lock prevention circuit to receive the reference signal, the first delayed signal, and the second delayed signal, and to adjust the delay time so that a period of each delayed signal is within a predetermined range.

    摘要翻译： 延迟锁定环路装置包括：第一延迟元件，用于接收参考信号，延迟参考信号延迟时间，并输出第一延迟信号。 第二延迟元件用于接收第一延迟信号，以将第一信号延迟信号延迟延迟时间，并输出第二延迟信号。 还包括接收参考信号，第一延迟信号和第二延迟信号的谐波锁定防止电路，并且调整延迟时间，使得每个延迟信号的周期在预定范围内。

    Frequency comparator with hysteresis between locked and unlocked conditions
    4.
    发明授权
    Frequency comparator with hysteresis between locked and unlocked conditions 有权
    频率比较器在锁定和解锁条件之间具有滞后

    公开(公告)号：US06859107B1

    公开(公告)日：2005-02-22

    申请号：US10356695

    申请日：2003-01-30

    申请人： Yongsam Moon ,  Gijung Ahn ,  Deog-Kyoon Jeong

    发明人： Yongsam Moon ,  Gijung Ahn ,  Deog-Kyoon Jeong

    IPC分类号： H03L7/091 ,  H03L7/113 ,  H03L7/14 ,  H04L7/033 ,  H04L7/04 ,  H03L7/095

    CPC分类号： H04L7/033 ,  H03L7/091 ,  H03L7/113 ,  H03L7/14 ,  H04L7/04 ,  Y10S331/02

    摘要： A frequency comparator apparatus used with a reference clock, a voltage controlled oscillator circuit and a phase locked loop circuit includes a reference loop circuit wherein the reference loop circuit is activated when the frequency difference between the reference clock and the voltage controlled oscillator circuit is greater than about a first threshold. Also included is a data loop circuit wherein the data loop circuit is activated when the frequency difference between the reference clock and the voltage controlled oscillator circuit is less than about a second threshold.

    摘要翻译： 与参考时钟，压控振荡器电路和锁相环电路一起使用的频率比较器装置包括参考环路电路，其中当参考时钟和压控振荡器电路之间的频率差大于 约第一个门槛。 还包括数据环路电路，其中当参考时钟和压控振荡器电路之间的频率差小于约第二阈值时，数据环路电路被激活。

    CMOS driver and on-chip termination for gigabaud speed data communication
    5.
    发明授权
    CMOS driver and on-chip termination for gigabaud speed data communication 有权
    CMOS驱动器和片上终端，用于千兆位速度数据通信

    公开(公告)号：US06560290B2

    公开(公告)日：2003-05-06

    申请号：US09234619

    申请日：1999-01-20

    申请人： Gijung Ahn ,  Deog-Kyoon Jeong ,  Gyudong Kim

    发明人： Gijung Ahn ,  Deog-Kyoon Jeong ,  Gyudong Kim

    IPC分类号： H04L2700

    CPC分类号： H04L25/028 ,  H04L25/0272 ,  H04L25/0292

    摘要： New very high-speed CMOS techniques are used to achieve a CMOS driver operating at gigabaud speeds. Such a driver may be manufactured more easily than drivers that use GaAs or bipolar techniques and further may be easily integrated with other CMOS circuits. A communication system utilizing the gigabaud CMOS driver may additionally include a receiver with on-chip termination to significantly reduce distortion in the presence of parasitic capacitance in inductance in comparison to a receiver with external termination. Furthermore, the communication system may include a phase tracker and a frame aligner. The phase tracker continously monitors the most frequent transition edges in the oversampled data so that the phase of the receiver clock keeps track of the sender clock. The frame aligner comprises a comma detector which enables instant synchronization of data words with a single comma character within a serial data stream.

    摘要翻译： 使用新的非常高速的CMOS技术来实现以千兆位速度运行的CMOS驱动器。 这样的驱动器可以比使用GaAs或双极技术的驱动器更容易制造，并且还可以容易地与其他CMOS电路集成。 与具有外部端接的接收机相比，使用千兆位CMOS驱动器的通信系统可以另外包括具有片上终止的接收器，以在存在电感中的寄生电容的情况下显着减少失真。 此外，通信系统可以包括相位跟踪器和帧对准器。 相位跟踪器连续监视过采样数据中最频繁的转换边沿，使得接收机时钟的相位跟踪发送器时钟。 帧对准器包括逗号检测器，该逗号检测器使串行数据流中具有单个逗号字符的数据字能够即时同步。

    System and method for high-speed, synchronized data communication
    6.
    发明授权
    System and method for high-speed, synchronized data communication 有权
    用于高速，同步数据通信的系统和方法

    公开(公告)号：US06587525B2

    公开(公告)日：2003-07-01

    申请号：US09814256

    申请日：2001-03-21

    申请人： Deog-Kyoon Jeong ,  Gijung Ahn

    发明人： Deog-Kyoon Jeong ,  Gijung Ahn

    IPC分类号： H04L700

    CPC分类号： H04L7/0334

    摘要： A system for transmission and recovery of original digital data includes an encoder, a transmitter, a receiver, a decoder, and an analog phase locked loop. The analog phase locked loop supplies a sender's clock to the transmitter and a receiver's clock to the receiver, where the sender's clock frequency is a first integer multiple of the system clock frequency, and the receiver's clock frequency is a second integer multiple of the sender's clock frequency within 0.1% tolerance. In a normal flow situation, data frames are output by the receiver in alternate cycles of the system clock. In an overflow situation, data frames are output by the receiver in consecutive cycles of the system clock. In an underflow situation, data frames are not output by the receiver in consecutive cycles of the system clock.

    摘要翻译： 用于传输和恢复原始数字数据的系统包括编码器，发射机，接收机，解码器和模拟锁相环。 模拟锁相环将发送器的时钟提供给发送器，并将接收器的时钟提供给接收器，其中发送器的时钟频率是系统时钟频率的第一个整数倍，接收器的时钟频率是发送器时钟的第二个整数倍 频率在0.1％以内。 在正常流量情况下，数据帧由系统时钟的交替周期由接收器输出。 在溢出情况下，数据帧由系统时钟的连续周期由接收器输出。 在下溢情况下，数据帧不会在系统时钟的连续周期内被接收机输出。

    System and method for high-speed, synchronized data communication
    7.
    发明授权
    System and method for high-speed, synchronized data communication 有权

    公开(公告)号：US06229859B1

    公开(公告)日：2001-05-08

    申请号：US09146818

    申请日：1998-09-04

    申请人： Deog-Kyoon Jeong ,  Gijung Ahn

    发明人： Deog-Kyoon Jeong ,  Gijung Ahn

    IPC分类号： H04L700

    CPC分类号： H04L7/0334

    摘要： A system for transmission and recovery of original digital data includes an encoder, a transmitter, a receiver, a decoder, and an analog phase locked loop. The analog phase locked loop supplies a sender's clock to the transmitter and a receiver's clock to the receiver, where the sender's clock frequency is a first integer multiple of the system clock frequency, and the receiver's clock frequency is a second integer multiple of the sender's clock frequency within 0.1% tolerance. In a normal flow situation, data frames are output by the receiver in alternate cycles of the system clock. In an overflow situation, data frames are output by the receiver in consecutive cycles of the system clock. In an underflow situation, data frames are not output by the receiver in consecutive cycles of the system clock.

    CMOS transceiver with dual current path VCO
    8.
    发明授权
    CMOS transceiver with dual current path VCO 有权
    具有双电流通道VCO的CMOS收发器

    公开(公告)号：US07551909B1

    公开(公告)日：2009-06-23

    申请号：US10651500

    申请日：2003-08-29

    申请人： Yongsam Moon ,  Young Soo Park ,  Deog-Kyoon Jeong

    发明人： Yongsam Moon ,  Young Soo Park ,  Deog-Kyoon Jeong

    IPC分类号： H04B1/06

    CPC分类号： H03L7/107 ,  H03L7/0812 ,  H03L7/087 ,  H03L7/0891 ,  H03L7/0995

    摘要： A dual current path voltage controlled oscillator exhibits both the seamless frequency acquisition and uniform VCO gain reduction while preserving an original operating range and phase locked loop characteristics. The present invention provides a quad-channel transceiver comprising a phase locked loop circuit including a voltage controlled oscillator used to generate a clock signal, a FIFO buffer used to store data to be transmitted, a frequency comparator for comparing a reference clock to the generated clock signal from the phase locked loop circuit; and a folded starved inverter circuit contained within the voltage controlled oscillator wherein the folded starved inverter provides two current paths. The dual current paths allow for simultaneous coarse and fine phase tracking. With this low jitter performance and wide operating range, the quad transceiver may be implemented in 0.18-μm CMOS technology, and shows 10−12 bit error rate up to speeds of 3 Gbps.

    摘要翻译： 双电流通道压控振荡器既保留了无缝频率采集和均匀的VCO增益降低，​​又保留了原始工作范围和锁相环特性。 本发明提供了一种四通道收发器，包括一个锁相环电路，该锁相环电路包括用于产生时钟信号的压控振荡器，用于存储要发送的数据的FIFO缓冲器，用于将参考时钟与所产生的时钟进行比较的频率比较器 来自锁相环电路的信号; 以及包含在压控振荡器内的折叠饥饿逆变器电路，其中折叠的饥饿逆变器提供两个电流路径。 双电流路径允许同步粗略和精细的相位跟踪。 凭借这种低抖动性能和广泛的工作范围，四通道收发器可以以0.18微米CMOS技术实现，并显示出10到12位的误码率，达到3 Gbps的速度。