公开(公告)号：US09147028B2

公开(公告)日：2015-09-29

申请号：US13902395

申请日：2013-05-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Mahbub Rashed ,  Lei Yuan

IPC: G06F17/50 ,  H01L29/66 ,  H01L29/78

CPC classification number: G06F17/5072 ,  G06F17/5068 ,  H01L21/823431 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/785 ,  Y02T10/82

Abstract: Methods for accommodating a non-integer multiple of the M2 pitch for the cell height of a semiconductor cell and the resulting devices are disclosed. Embodiments may include forming a cell within an integrated circuit (IC) with a height of a first integer and a remainder times a track pitch of a metal track layer, and forming power rails within the metal track layer at boundaries of the cell accommodating for the remainder.

Abstract translation: 公开了用于容纳用于半导体单元的单元高度的M2间距的非整数倍的方法以及所得到的器件。 实施例可以包括在具有第一整数和余数乘以金属轨道层的轨道间距的集成电路（IC）内形成单元，以及在金属轨道层的边界处形成用于为 余。

公开(公告)号：US09122830B2

公开(公告)日：2015-09-01

申请号：US13908096

申请日：2013-06-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Yuan ,  Juhan Kim ,  Jongwook Kye ,  Mahbub Rashed

IPC: H01L27/02 ,  G06F17/50 ,  H01L27/118 ,  H01L23/522

CPC classification number: G06F17/5077 ,  H01L23/5226 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments described herein provide approaches for improved circuit routing using a wide-edge pin. Specifically, provided is an integrated circuit (IC) device comprising a standard cell having a first metal layer (M1) pin coupled to a second metal layer (M2) wire at a via. The M1 pin has a width greater than a width of the via sufficient to satisfy an enclosure rule for the via, while the M1 pin extends vertically past the via a distance substantially equal to or greater than zero. This layout increases the number of available pin access points within the standard cell and thus improves routing efficiency and chip size.

Abstract translation: 本文描述的实施例提供了使用宽边缘引脚改进电路布线的方法。 具体地，提供了一种集成电路（IC）装置，其包括具有在通孔处耦合到第二金属层（M2）线的第一金属层（M1）引脚的标准单元。 M1引脚的宽度大于通孔的宽度，足以满足通孔的外壳规则，而M1引脚垂直延伸超过基本上等于或大于零的距离。 该布局增加了标准单元内可用引脚接入点的数量，从而提高了布线效率和芯片尺寸。

公开(公告)号：US20150108583A1

公开(公告)日：2015-04-23

申请号：US14579628

申请日：2014-12-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mahbub Rashed ,  Johan Kim ,  Yunfei Deng ,  Suresh Venkatesan

IPC: H01L29/06 ,  H01L29/78 ,  H01L27/088

CPC classification number: H01L29/0696 ,  G06F17/5072 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/6681 ,  H01L29/785

Abstract: One method disclosed herein includes forming first and second transistor devices in and above adjacent active regions that are separated by an isolation region, wherein the transistors comprise a source/drain region and a shared gate structure, forming a continuous conductive line that spans across the isolation region and contacts the source/drain regions of the transistors and etching the continuous conductive line to form separated first and second unitary conductive source/drain contact structures that contact the source/drain regions of the first and second transistors, respectively. A device disclosed herein includes a gate structure, source/drain regions, first and second unitary conductive source/drain contact structures, each of which contacts one of the source/drain regions, and first and second conductive vias that contact the first and second unitary conductive source/drain contact structures, respectively

Abstract translation: 本文公开的一种方法包括在由隔离区域分隔的相邻有源区域中和上方形成第一和第二晶体管器件，其中晶体管包括源极/漏极区域和共享栅极结构，形成跨越隔离的连续导电线 区域并与晶体管的源极/漏极区域接触并蚀刻连续导电线以形成分别与第一和第二晶体管的源极/漏极区域接触的分离的第一和第二整体导电源极/漏极接触结构。 本文公开的器件包括栅极结构，源极/漏极区域，第一和第二整体导电源极/漏极接触结构，其每一个接触源极/漏极区域之一，以及接触第一和第二整体的第一和第二导电通孔 导电源极/漏极接触结构

公开(公告)号：US08916441B2

公开(公告)日：2014-12-23

申请号：US13893684

申请日：2013-05-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mahbub Rashed ,  Juhan Kim ,  Yunfei Deng ,  Jongwook Kye ,  Suresh Venkatesan

IPC: H01L21/8234 ,  H01L21/8244 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/6681

Abstract: Embodiments of the present invention provide a novel method and structure for forming finFET structures that comprise standard cells. An H-shaped cut mask is used to reduce the number of fins that need to be removed, hence increasing the fin efficiency.

Abstract translation: 本发明的实施例提供了用于形成包含标准单元的finFET结构的新颖方法和结构。 使用H形切割掩模来减少需要去除的翅片的数量，从而提高翅片效率。

公开(公告)号：US20140353842A1

公开(公告)日：2014-12-04

申请号：US13908096

申请日：2013-06-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Yuan ,  Juhan Kim ,  Jongwook Kye ,  Mahbub Rashed

IPC: G06F17/50 ,  H01L23/522

CPC classification number: G06F17/5077 ,  H01L23/5226 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments described herein provide approaches for improved circuit routing using a wide-edge pin. Specifically, provided is an integrated circuit (IC) device comprising a standard cell having a first metal layer (M1) pin coupled to a second metal layer (M2) wire at a via. The M1 pin has a width greater than a width of the via sufficient to satisfy an enclosure rule for the via, while the M1 pin extends vertically past the via a distance substantially equal to or greater than zero. This layout increases the number of available pin access points within the standard cell and thus improves routing efficiency and chip size.

Abstract translation: 本文描述的实施例提供了使用宽边缘引脚改进电路布线的方法。 具体地，提供了一种集成电路（IC）装置，其包括具有在通孔处连接到第二金属层（M2）线的第一金属层（M1）引脚的标准单元。 M1引脚的宽度大于通孔的宽度，足以满足通孔的外壳规则，而M1引脚垂直延伸超过基本上等于或大于零的距离。 该布局增加了标准单元内可用引脚接入点的数量，从而提高了布线效率和芯片尺寸。

公开(公告)号：US20140339610A1

公开(公告)日：2014-11-20

申请号：US13893684

申请日：2013-05-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Mahbub Rashed ,  Juhan Kim ,  Yunfei Deng ,  Jongwook Kye ,  Suresh Venkatesan

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/6681

Abstract: Embodiments of the present invention provide a novel method and structure for forming finFET structures that comprise standard cells. An H-shaped cut mask is used to reduce the number of fins that need to be removed, hence increasing the fin efficiency.

Abstract translation: 本发明的实施例提供了用于形成包含标准单元的finFET结构的新颖方法和结构。 使用H形切割掩模来减少需要去除的翅片的数量，从而提高翅片效率。

公开(公告)号：US08789000B1

公开(公告)日：2014-07-22

申请号：US13863591

申请日：2013-04-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mahbub Rashed ,  Lei Yuan ,  Jongwook Kye ,  Suresh Venkatesan

IPC: G06F17/50

CPC classification number: G06F17/5077

Abstract: A system and design methodology for performing routing in an integrated circuit design is disclosed. An integrated circuit design is first created using standard cells having metal level 2 (M2) power rails. Routing is performed and power rail current density for the integrated circuit is computed. Standard cells that have power rail current density below a predetermined threshold are replaced with a functionally equivalent standard cell that does not have M2 power rails, and the routing operation is performed again, until the design converges.

Abstract translation: 公开了一种用于在集成电路设计中执行路由的系统和设计方法。 首先使用具有金属级2（M2）电源轨的标准单元创建集成电路设计。 执行路由，并计算集成电路的电源轨电流密度。 具有低于预定阈值的电力轨电流密度的标准电池被替换为不具有M2电力轨的功能等效的标准单元，并且直到设计收敛为止，再次执行路由操作。