公开(公告)号：US11264470B2

公开(公告)日：2022-03-01

申请号：US16803711

申请日：2020-02-27

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Haiting Wang ,  Tamilmani Ethirajan ,  Zhenyu Hu ,  Tung-Hsing Lee

IPC: H01L29/417 ,  H01L29/08 ,  H01L29/73 ,  H01L29/10 ,  H01L29/423

Abstract: One illustrative device disclosed herein includes a semiconductor substrate and a bipolar junction transistor (BJT) device that comprises a collector region, a base region and an emitter region. In this example, the device also includes a field effect transistor and at least one base conductive contact structure that conductively and physically contacts the base region.

公开(公告)号：US20220059691A1

公开(公告)日：2022-02-24

申请号：US16996010

申请日：2020-08-18

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Yanping Shen ,  Haiting Wang ,  Zhiqing Li

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08

Abstract: Disclosed is a lateral double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) with a replacement metal gate (RMG) structure that includes a first section, which traverses a semiconductor body at a channel region in a first-type well, and a second section, which is adjacent to the first section and which traverses the semiconductor body at a drain drift region in a second-type well. The RMG structure includes, in both sections, a first-type work function layer and a second-type work function layer on the first-type work function layer. However, the thickness of the first-type work function layer in the first section is greater than the thickness in the second section such that the RMG structure is asymmetric. Thus, threshold voltage (Vt) at the first section is greater than Vt at the second section and the LDMOSFET has a relatively high breakdown voltage (BV). Also disclosed are methods for forming the LDMOSFET.

公开(公告)号：US20210320207A1

公开(公告)日：2021-10-14

申请号：US16843421

申请日：2020-04-08

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Haiting Wang ,  Judson R. Holt ,  Sipeng Gu

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02

Abstract: A structure for a field-effect transistor includes a semiconductor body, a first gate structure extending over the semiconductor body, and a second gate structure extending over the semiconductor body. A recess is in the semiconductor body between the first and second gate structures. A three part source/drain region includes a pair of spaced semiconductor spacers in the recess; a first semiconductor layer laterally between the pair of semiconductor spacers; and a second semiconductor layer over the first semiconductor layer. The pair of spaced semiconductor spacers, the first semiconductor layer and the second semiconductor layer may all have different dopant concentrations.

公开(公告)号：US20210313321A1

公开(公告)日：2021-10-07

申请号：US16842075

申请日：2020-04-07

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Haiting Wang ,  Sipeng Gu ,  Shesh Mani Pandey ,  Lixia Lei ,  Gregory Costrini

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L27/092 ,  H01L21/8234

Abstract: One illustrative device disclosed herein includes at least one fin structure and an isolation structure comprising a stepped upper surface comprising a first region and a second region. The first region has a first upper surface and the second region has a second upper surface, wherein the first upper surface is positioned at a first level and the second upper surface is positioned at a second level and wherein the first level is below the second level. In this illustrative example, the device also includes a gate structure comprising a first portion and a second portion, wherein the first portion of the gate structure is positioned above the first upper surface of the isolation structure and above the at least one fin structure and wherein the second portion of the gate structure is positioned above the second upper surface of the isolation structure.

公开(公告)号：US20210305495A1

公开(公告)日：2021-09-30

申请号：US16836434

申请日：2020-03-31

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Yanping Shen ,  Haiting Wang ,  Sipeng Gu

IPC: H01L43/02 ,  H01L43/12 ,  G11C11/16 ,  H01L27/22

Abstract: One illustrative memory cell disclosed herein includes at least one layer of insulating material having a first opening and an internal sidewall spacer positioned within the first opening, wherein the internal sidewall spacer includes a spacer opening. The memory cell also includes a bottom electrode positioned within the spacer opening, a memory state material positioned above an upper surface of the bottom electrode and above an upper surface of the internal sidewall spacer, and a top electrode positioned above the memory state material.

公开(公告)号：US20210111065A1

公开(公告)日：2021-04-15

申请号：US16596814

申请日：2019-10-09

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Yongjun Shi ,  Wei Hong ,  Chun Yu Wong ,  Haiting Wang ,  Liu Jiang

IPC: H01L21/762 ,  H01L27/12

Abstract: A method and related structure provide a void-free dielectric over trench isolation region in an FDSOI substrate. The structure may include a first transistor including a first active gate over the substrate, a second transistor including a second active gate over the substrate, a first liner extending over the first transistor, and a second, different liner extending over the second transistor. A trench isolation region electrically isolates the first transistor from the second transistor. The trench isolation region includes a trench isolation extending into the FDSOI substrate and an inactive gate over the trench isolation. A dielectric extends over the inactive gate and in direct contact with an upper surface of the trench isolation region. The dielectric is void-free, and the liners do not extend over the trench isolation.

公开(公告)号：US12205949B1

公开(公告)日：2025-01-21

申请号：US18758069

申请日：2024-06-28

Applicant: GlobalFoundries U.S. Inc.

Inventor： Zhenyu Hu ,  Hong Yu ,  Haiting Wang

IPC: H01L27/088 ,  H01L27/06 ,  H01L29/40 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

Abstract: Device structures for a high-voltage semiconductor device and methods of forming such device structures. The structure comprises a semiconductor substrate and a layer stack including a first dielectric layer and a second dielectric layer. The first dielectric layer is positioned between the second dielectric layer and the semiconductor substrate. The structure further comprises a field-effect transistor including a first source/drain region in the semiconductor substrate, a second source/drain region in the semiconductor substrate, and a metal gate on the layer stack laterally between the first source/drain region and the second source/drain region. The second dielectric layer is positioned between the metal gate and the first dielectric layer. A contact extends through the layer stack to the first source/drain region.

公开(公告)号：US11990535B2

公开(公告)日：2024-05-21

申请号：US17511613

申请日：2021-10-27

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Alexander M. Derrickson ,  Haiting Wang ,  Judson R. Holt ,  Vibhor Jain ,  Richard F. Taylor, III

IPC: H01L29/737 ,  H01L21/02 ,  H01L21/225 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/737 ,  H01L21/02532 ,  H01L21/2251 ,  H01L29/0808 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/165 ,  H01L29/66242

Abstract: Disclosed is a semiconductor structure including a lateral heterojunction bipolar transistor (HBT). The structure includes a substrate (e.g., a silicon substrate), an insulator layer on the substrate, and a semiconductor layer (e.g., a silicon germanium layer) on the insulator layer. The structure includes a lateral HBT with three terminals including a collector, an emitter, and a base, which is positioned laterally between the collector and the emitter and which can include a silicon germanium intrinsic base region for improved performance. Additionally, the collector and/or the emitter includes: a first region, which is epitaxially grown within a trench that extends through the semiconductor layer and the insulator layer to the substrate; and a second region, which is epitaxially grown on the first region. The connection(s) of the collector and/or the emitter to the substrate effectively form thermal exit path(s) and minimize self-heating. Also disclosed is a method for forming the structure.

公开(公告)号：US11908898B2

公开(公告)日：2024-02-20

申请号：US17456943

申请日：2021-11-30

Applicant: GlobalFoundries U.S. Inc.

Inventor： Haiting Wang ,  Hong Yu ,  Zhenyu Hu ,  Alexander M. Derrickson

IPC: H01L29/10 ,  H01L29/735 ,  H01L29/66

CPC classification number: H01L29/1008 ,  H01L29/6625 ,  H01L29/735

Abstract: Embodiments of the disclosure provide a lateral bipolar transistor with a base layer of varying horizontal thickness, and related methods to form the same. A lateral bipolar transistor may include an emitter/collector (E/C) layer on a semiconductor layer. A first base layer is on the semiconductor layer and horizontally adjacent the E/C layer. The first base layer has a lower portion having a first horizontal width from the E/C layer. The first base layer also has an upper portion on the lower portion, with a second horizontal width from the E/C layer greater than the first horizontal width. A second base layer is on the first base layer and adjacent a spacer. The upper portion of the first base layer separates a lower surface of the second base layer from the E/C layer.

公开(公告)号：US11785860B2

公开(公告)日：2023-10-10

申请号：US16846497

申请日：2020-04-13

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Sipeng Gu ,  Haiting Wang ,  Yanping Shen

IPC: H10N50/80 ,  H10B51/30 ,  H10B53/30 ,  H10B61/00 ,  H10B63/00 ,  H10N50/01 ,  H10N50/10 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10N50/80 ,  H10B51/30 ,  H10B53/30 ,  H10B61/00 ,  H10B63/00 ,  H10N50/01 ,  H10N50/10 ,  H10N70/011 ,  H10N70/231 ,  H10N70/841

Abstract: One illustrative device disclosed herein includes a memory cell positioned in a first opening in at least one layer of insulating material. The memory cell comprises a bottom electrode, a memory state material positioned above the bottom electrode and an internal sidewall spacer positioned within the first opening, wherein the internal sidewall spacer defines a spacer opening. The device also comprises a top electrode positioned within the spacer opening.