公开(公告)号：US06803631B2

公开(公告)日：2004-10-12

申请号：US10349042

申请日：2003-01-23

Applicant: Srikanteswara Dakshina-Murthy ,  Judy Xilin An ,  Zoran Krivokapic ,  Haihong Wang ,  Bin Yu

Inventor： Srikanteswara Dakshina-Murthy ,  Judy Xilin An ,  Zoran Krivokapic ,  Haihong Wang ,  Bin Yu

IPC: H01L2701

CPC classification number: H01L29/785 ,  H01L29/1054 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/78654 ,  H01L29/78687

Abstract: A semiconductor structure includes a fin and a layer formed on the fin. The fin includes a first crystalline material having a rectangular cross section and a number of surfaces. The layer is formed on the surfaces and includes a second crystalline material. The first crystalline material has a different lattice constant than the second crystalline material to induce tensile strain within the first layer.

Abstract translation: 半导体结构包括翅片和形成在翅片上的层。 翅片包括具有矩形横截面和多个表面的第一结晶材料。 该层形成在表面上并且包括第二结晶材料。 第一结晶材料具有与第二结晶材料不同的晶格常数，以在第一层内引起拉伸应变。

公开(公告)号：US06787854B1

公开(公告)日：2004-09-07

申请号：US10385753

申请日：2003-03-12

Applicant: Chih-Yuh Yang ,  Shibly S. Ahmed ,  Srikanteswara Dakshina-Murthy ,  Cyrus E. Tabery ,  Haihong Wang ,  Bin Yu

Inventor： Chih-Yuh Yang ,  Shibly S. Ahmed ,  Srikanteswara Dakshina-Murthy ,  Cyrus E. Tabery ,  Haihong Wang ,  Bin Yu

IPC: H01L218238

CPC classification number: H01L29/7853 ,  H01L29/66818

Abstract: A method for forming a fin structure on a silicon-on-insulator (SOI) wafer that includes a silicon layer on an insulating layer that is formed over a semiconductor substrate includes etching the silicon layer using a first etch procedure, etching, following the first etch procedure, the silicon layer using a second etch procedure, and etching, following the second etch procedure, the silicon layer using a third etch procedure to form a T-shaped fin structure.

Abstract translation: 一种在绝缘体上硅（SOI）晶片上形成翅片结构的方法，包括在半导体衬底上形成的绝缘层上的硅层，包括使用第一蚀刻步骤蚀刻硅层，然后蚀刻第一 蚀刻步骤，使用第二蚀刻步骤的硅层，以及在第二蚀刻程序之后，使用第三蚀刻工艺蚀刻硅层以形成T形翅片结构。

公开(公告)号：US06762448B1

公开(公告)日：2004-07-13

申请号：US10405343

申请日：2003-04-03

Applicant: Ming-Ren Lin ,  Haihong Wang ,  Bin Yu

Inventor： Ming-Ren Lin ,  Haihong Wang ,  Bin Yu

IPC: H01L2708

CPC classification number: H01L29/785 ,  H01L21/823412 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/66795 ,  H01L29/7842

Abstract: A semiconductor device includes a group of fin structures. The group of fin structures includes a conductive material and is formed by growing the conductive material in an opening of an oxide layer. The semiconductor device further includes a source region formed at one end of the group of fin structures, a drain region formed at an opposite end of the group of fin structures, and at least one gate.

Abstract translation: 半导体器件包括一组翅片结构。 翅片结构的组包括导电材料，并且通过在氧化物层的开口中生长导电材料而形成。 半导体器件还包括形成在鳍片结构组的一端处的源极区域，形成在鳍片结构组的相对端处的漏极区域和至少一个栅极。

公开(公告)号：US06657223B1

公开(公告)日：2003-12-02

申请号：US10282538

申请日：2002-10-29

Applicant: Haihong Wang ,  Qi Xiang

Inventor： Haihong Wang ,  Qi Xiang

IPC: H01L2906

CPC classification number: H01L29/66431 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/66492 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/802

Abstract: A strained silicon MOSFET utilizes a strained silicon layer formed on a silicon germanium layer. Strained silicon and silicon germanium are removed at opposing sides of the gate and are replaced by silicon regions. Deep source and drain regions are implanted in the silicon regions, and the depth of the deep source and drain regions does not extend beyond the depth of the silicon regions. By forming the deep source and drain regions in the silicon regions, detrimental effects of the higher dielectric constant and lower band gap of silicon germanium are reduced.

Abstract translation: 应变硅MOSFET利用在硅锗层上形成的应变硅层。 应变硅和硅锗在栅极的相对侧被去除并被硅区域代替。 深源极和漏极区域被注入到硅区域中，并且深源极和漏极区域的深度不延伸超过硅区域的深度。 通过在硅区域形成深源极和漏极区域，降低了硅锗的较高介电常数和较低带隙的有害影响。

公开(公告)号：US08554725B2

公开(公告)日：2013-10-08

申请号：US13477999

申请日：2012-05-22

Applicant: Haihong Wang

Inventor： Haihong Wang

IPC: G06F17/30

CPC classification number: G06F17/30174 ,  Y10S707/99952

Abstract: Data replication includes generating replication data that is part of a replicated file system to be sent over a communication channel to a destination replication device; adding additional verification information to at least a portion of the replication data to prevent data corruption; and sending the replication data and the additional verification information over the communication channel to the destination replication device. The replication data with additional verification information is sent over the communication channel using a reliable protocol that allows the replication data to be verified by the reliable protocol at the destination replication device. The reliable protocol is a protocol capable of detecting most but not all data corruption introduced by the communication channel. The additional verification information includes information for verifying that replication data sent using the reliable protocol does not include data corruption that was introduced by the communication channel and undetected by the reliable protocol.

Abstract translation: 数据复制包括生成作为通过通信通道发送到目标复制设备的复制文件系统的一部分的复制数据; 向至少一部分复制数据添加其他验证信息，以防止数据损坏; 以及通过所述通信信道将所述复制数据和所述附加验证信息发送到所述目的地复制设备。 具有附加验证信息的复制数据通过通信通道使用可靠的协议发送，该协议允许复制数据由目的地复制设备上的可靠协议进行验证。 可靠的协议是能够检测通信信道引入的大多数但不是全部数据损坏的协议。 附加验证信息包括用于验证使用可靠协议发送的复制数据不包括由通信信道引入并且不被可靠协议检测到的数据损坏的信息。

公开(公告)号：US08334181B1

公开(公告)日：2012-12-18

申请号：US12836378

申请日：2010-07-14

Applicant: Judy Xilin An ,  Zoran Krivokapic ,  Haihong Wang ,  Bin Yu

Inventor： Judy Xilin An ,  Zoran Krivokapic ,  Haihong Wang ,  Bin Yu

IPC: H01L29/72

CPC classification number: H01L29/7855 ,  H01L21/823821 ,  H01L29/42384 ,  H01L29/7843 ,  H01L29/78684

Abstract: A double gate germanium metal-oxide semiconductor field-effect transistor (MOSFET) includes a germanium fin, a first gate formed adjacent a first side of the germanium fin, and a second gate formed adjacent a second side of the germanium fin opposite the first side. A triple gate MOSFET includes a germanium fin, a first gate formed adjacent a first side of the germanium fin, a second gate formed adjacent a second side of the germanium fin opposite the first side, and a top gate formed on top of the germanium fin. An all-around gate MOSFET includes a germanium fin, a first sidewall gate structure formed adjacent a first side of the germanium fin, a second sidewall gate structure formed adjacent a second side of the germanium fin, and additional gate structures formed on and around the germanium fin.

Abstract translation: 双栅极锗金属氧化物半导体场效应晶体管（MOSFET）包括锗翅片，邻近锗翅片的第一侧形成的第一栅极和与第一侧相对的锗翅片第二侧附近形成的第二栅极 。 三栅极MOSFET包括锗翅片，与锗翅片的第一侧相邻形成的第一栅极，与第一侧相对的锗翅片的第二侧附近形成的第二栅极和形成在锗翅片顶部上的顶栅极 。 全栅极MOSFET包括锗翅片，邻近锗翅片的第一侧形成的第一侧壁栅极结构，邻近锗翅片的第二侧形成的第二侧壁栅极结构，以及形成在锗翅片上和周围的附近的栅极结构 锗鳍

公开(公告)号：US07701019B2

公开(公告)日：2010-04-20

申请号：US11356606

申请日：2006-02-17

Applicant: Minh V. Ngo ,  Paul R. Besser ,  Ming Ren Lin ,  Haihong Wang

Inventor： Minh V. Ngo ,  Paul R. Besser ,  Ming Ren Lin ,  Haihong Wang

IPC: H01L27/088

CPC classification number: H01L29/7843 ,  H01L29/1054 ,  H01L2924/0002 ,  Y10S257/90 ,  Y10S438/933 ,  H01L2924/00

Abstract: An exemplary embodiment relates to a method for forming a metal oxide semiconductor field effect transistor (MOSFET). The method includes providing a substrate having a gate formed above the substrate and performing at least one of the following depositing steps: depositing a spacer layer and forming a spacer around a gate and gate insulator located above a layer of silicon above the substrate; depositing an etch stop layer above the spacer, the gate, and the layer of silicon; and depositing a dielectric layer above the etch stop layer. At least one of the depositing a spacer layer, depositing an etch stop layer, and depositing a dielectric layer comprises high compression deposition which increases in tensile strain in the layer of silicon.

Abstract translation: 示例性实施例涉及形成金属氧化物半导体场效应晶体管（MOSFET）的方法。 该方法包括提供一个衬底，该衬底具有形成在衬底上方的栅极，并且执行以下沉积步骤中的至少一个：在位于衬底上方的硅层上方的栅极和栅绝缘体周围沉积间隔层并形成间隔物; 在间隔物，栅极和硅层之上沉积蚀刻停止层; 以及在所述蚀刻停止层上沉积介电层。 沉积间隔层，沉积蚀刻停止层和沉积介电层中的至少一个包括增加硅层中的拉伸应变的高压缩沉积。

公开(公告)号：US07498225B1

公开(公告)日：2009-03-03

申请号：US11428722

申请日：2006-07-05

Applicant: Haihong Wang ,  Shibly S. Ahmed ,  Ming-Ren Lin ,  Bin Yu

Inventor： Haihong Wang ,  Shibly S. Ahmed ,  Ming-Ren Lin ,  Bin Yu

IPC: H01L21/336 ,  H01L21/3205 ,  H01L21/4763

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/02672 ,  H01L29/785

Abstract: A method for forming fin structures for a semiconductor device that includes a substrate and a dielectric layer formed on the substrate is provided. The method includes etching the dielectric layer to form a first structure, depositing an amorphous silicon layer over the first structure, and etching the amorphous silicon layer to form second and third fin structures adjacent first and second side surfaces of the first structure. The second and third fin structures may include amorphous silicon material. The method further includes depositing a metal layer on upper surfaces of the second and third fin structures, performing a metal-induced crystallization operation to convert the amorphous silicon material of the second and third fin structures to a crystalline silicon material, and removing the first structure.

Abstract translation: 提供了一种用于形成半导体器件的鳍结构的方法，该半导体器件包括衬底和形成在衬底上的电介质层。 该方法包括蚀刻介电层以形成第一结构，在第一结构上沉积非晶硅层，以及蚀刻非晶硅层以形成与第一结构的第一和第二侧表面相邻的第二和第三鳍结构。 第二和第三鳍结构可以包括非晶硅材料。 该方法还包括在第二和第三鳍结构的上表面上沉积金属层，执行金属诱导结晶操作以将第二鳍和第三鳍结构的非晶硅材料转化成晶体硅材料，并且去除第一结构 。

公开(公告)号：US20090047770A1

公开(公告)日：2009-02-19

申请号：US12205361

申请日：2008-09-05

Applicant: Haihong Wang ,  Minh-Van Ngo ,  Qi Xiang ,  Paul R. Besser ,  Eric N. Paton ,  Ming-Ren Lin

Inventor： Haihong Wang ,  Minh-Van Ngo ,  Qi Xiang ,  Paul R. Besser ,  Eric N. Paton ,  Ming-Ren Lin

IPC: H01L21/76

CPC classification number: H01L21/76224 ,  H01L21/823481 ,  H01L29/1054

Abstract: A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed from a semiconductor or metal layer which is deposited in a low temperature process which reduces germanium outgassing. The low temperature process can be a ALD process.

Abstract translation: 集成电路（IC）的制造方法利用浅沟槽隔离（STI）技术。 浅沟槽隔离技术用于应变硅（SMOS）工艺。 用于沟槽的衬垫由半导体或金属层形成，该半导体或金属层在低温过程中沉积，这降低了锗除气。 低温过程可以是ALD过程。

公开(公告)号：US07279735B1

公开(公告)日：2007-10-09

申请号：US10838215

申请日：2004-05-05

Applicant: Bin Yu ,  Haihong Wang

Inventor： Bin Yu ,  Haihong Wang

IPC: H01L29/788

CPC classification number: H01L29/7883 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/785

Abstract: A non-volatile memory device includes a substrate, an insulating layer, a fin structure, a floating gate, an inter-gate dielectric and a control gate. The insulating layer is formed on the substrate and the fin structure is formed on the insulating layer. The fin structure may include a strained layer formed on a non-strained layer.

Abstract translation: 非易失性存储器件包括衬底，绝缘层，翅片结构，浮动栅极，栅极间电介质和控制栅极。 绝缘层形成在基板上，翅片结构形成在绝缘层上。 翅片结构可以包括形成在非应变层上的应变层。