公开(公告)号：US07688242B2

公开(公告)日：2010-03-30

申请号：US12076270

申请日：2008-03-14

申请人： Kazuya Shimizu ,  Haruo Kobayashi ,  Koichiro Mashiko

发明人： Kazuya Shimizu ,  Haruo Kobayashi ,  Koichiro Mashiko

IPC分类号： H03M1/12

CPC分类号： H03M1/0836 ,  G04F10/005 ,  H03M1/502

摘要： An AD converter that operates at high speed and precision of which is disclosed. The AD converter includes an analog-to-digital (AD) conversion part that samples an analog signal according to a sampling clock and converts it into a digital signal, a jitter measuring circuit that measures the jitter of the sampling clock, and a correction circuit that corrects a digital signal output from the AD conversion part. The AD converter further comprises a clock source and a sampling generating circuit that generates a sampling clock by dividing the clock generated by the clock source, wherein the jitter measuring circuit measures the jitter of the sampling clock with respect to the click on the basis of a clock CK.

摘要翻译： 公开了以高速度和精度工作的AD转换器。 AD转换器包括模数（AD）转换部分，其根据采样时钟对模拟信号进行采样并将其转换为数字信号，测量采样时钟的抖动的抖动测量电路和校正电路 其校正从AD转换部分输出的数字信号。 AD转换器还包括时钟源和采样发生电路，其通过对由时钟源产生的时钟进行分频来产生采样时钟，其中抖动测量电路基于以下步骤测量采样时钟相对于咔嗒声的抖动： 时钟CK。

公开(公告)号：US20090225631A1

公开(公告)日：2009-09-10

申请号：US12382056

申请日：2009-03-06

申请人： Kazuya shimizu ,  Masato Kaneta ,  Haruo Kobayashi ,  Tatsuji Matsuura ,  Katsuyoshi Yagi ,  Akira Abe ,  Koichiro Mashiko

发明人： Kazuya shimizu ,  Masato Kaneta ,  Haruo Kobayashi ,  Tatsuji Matsuura ,  Katsuyoshi Yagi ,  Akira Abe ,  Koichiro Mashiko

IPC分类号： G04F10/00

CPC分类号： G04F10/06

摘要： A TDC circuit having a small scale circuit and high resolution is disclosed, which is a time-to-digital converter that detects a phase with respect to a reference clock of a signal to be measured, comprising a first delay line in which a plurality of first delay elements with a first delay amount is connected in series, a second delay line group that is connected to a plurality of connection nodes of the first delay line or an input node in the first stage and in which at least one or more second delay elements with a second delay amount different from the first delay amount are connected in series, a plurality of judgment circuits that judge whether the changing edge of the signal to be measured is advanced or delayed with respect to the changing edges of a delayed clock output from the first delay element and the second delay element, and an operation circuit that calculates a phase with respect to the reference clock of the changing edge of the signal to be measured from the judgment results, wherein a difference between the first delay amount and the second delay amount is smaller than the first delay amount and the second delay amount.

摘要翻译： 公开了具有小尺度电路和高分辨率的TDC电路，其是检测相对于待测信号的参考时钟的相位的时间到数字转换器，包括第一延迟线，其中多个 具有第一延迟量的第一延迟元件被串联连接，第二延迟线组连接到第一延迟线的多个连接节点或第一级中的输入节点，并且其中至少一个或多个第二延迟 具有与第一延迟量不同的第二延迟量的元件串联连接;多个判断电路，用于判断待测信号的变化边沿是否相对于从...的延迟时钟输出的变化沿提前或延迟 第一延迟元件和第二延迟元件，以及操作电路，其从判断器计算相对于待测信号的变化边沿的参考时钟的相位 t结果，其中第一延迟量和第二延迟量之间的差小于第一延迟量和第二延迟量。

公开(公告)号：US20080238752A1

公开(公告)日：2008-10-02

申请号：US12076270

申请日：2008-03-14

申请人： Kazuya Shimizu ,  Haruo Kobayashi ,  Koichiro Mashiko

发明人： Kazuya Shimizu ,  Haruo Kobayashi ,  Koichiro Mashiko

IPC分类号： H03M1/12

CPC分类号： H03M1/0836 ,  G04F10/005 ,  H03M1/502

摘要： An AD converter that operates at high speed and precision of which is disclosed. The AD converter includes an analog-to-digital (AD) conversion part that samples an analog signal according to a sampling clock and converts it into a digital signal, a jitter measuring circuit that measures the jitter of the sampling clock, and a correction circuit that corrects a digital signal output from the AD conversion part. The AD converter further comprises a clock source and a sampling generating circuit that generates a sampling clock by dividing the clock generated by the clock source, wherein the jitter measuring circuit measures the jitter of the sampling clock with respect to the click on the basis of a clock CK.

摘要翻译： 公开了以高速度和精度工作的AD转换器。 AD转换器包括模数（AD）转换部分，其根据采样时钟对模拟信号进行采样并将其转换为数字信号，测量采样时钟的抖动的抖动测量电路和校正电路 其校正从AD转换部分输出的数字信号。 AD转换器还包括时钟源和采样发生电路，其通过对由时钟源产生的时钟进行分频来产生采样时钟，其中抖动测量电路基于以下步骤测量采样时钟相对于点击的抖动： 时钟CK。

公开(公告)号：US07242337B2

公开(公告)日：2007-07-10

申请号：US11408951

申请日：2006-04-24

申请人： Masafumi Uemori ,  Haruo Kobayashi ,  Tomonari Ichikawa ,  Koichiro Mashiko

发明人： Masafumi Uemori ,  Haruo Kobayashi ,  Tomonari Ichikawa ,  Koichiro Mashiko

IPC分类号： H03M3/00

CPC分类号： H03M3/372 ,  H03M3/402 ,  H03M3/422 ,  H03M3/454 ,  H03M3/496

摘要： A continuous-time band-pass ΔΣ AD modulator subtracts an analog signal from a DA converter from an inputted analog signal, outputs an analog signal having a subtraction result to an AD converter via a continuous-time analog band-pass filter, outputs a digital signal from the AD converter to the DA converter, and outputs the same digital signal as a digital signal subjected to a band-pass ΔΣ AD modulation processing. The highest input frequency “fin” of the inputted analog signal is substantially set to three-fourths of a sampling frequency “fs”. The DA converter is configured to convert the inputted digital signal into the analog signal, and outputs the analog signal, which is inverted or not in response to a value of the inputted digital signal and has an amplitude of substantially zero and a gradient of substantially zero at a timing k/(2fs).

摘要翻译： 连续时间带通DeltaSigma AD调制器从输入的模拟信号中减去来自DA转换器的模拟信号，经由连续时间模拟带通滤波器将具有减法结果的模拟信号输出到AD转换器，输出数字 信号从AD转换器传送到DA转换器，并输出与进行带通DeltaSigma AD调制处理的数字信号相同的数字信号。 输入的模拟信号的最高输入频率“fin”基本上被设置为采样频率“fs”的四分之三。 DA转换器被配置为将输入的数字信号转换为模拟信号，并且输出模拟信号，该模拟信号被反相或不响应于输入的数字信号的值，并且具有基本为零的幅度和基本为零的梯度 在k /（2fs）的时刻。

公开(公告)号：US06832107B2

公开(公告)日：2004-12-14

申请号：US09877183

申请日：2001-06-11

申请人： Koichiro Mashiko

发明人： Koichiro Mashiko

IPC分类号： H04B138

CPC分类号： H02J7/0027 ,  H02J7/00 ,  H02J2007/0096 ,  H04B1/3883 ,  H04M1/7253 ,  H04M1/727

摘要： A portable information system having an information registration function achieves reduction in manufacturing cost and power consumption. By connecting portable information equipment (1) and a battery charger (10) to be chargeable, signal transmission becomes possible between a micro controller (2) in the portable information equipment (1) and a micro controller (11) in the battery charger (10). Under the control of the micro controllers (2, 11), information management operation is automatically performed during charging. The operation includes backup processing in which personal information stored in a storage portion (3) in the portable information equipment (1) is transferred to a storage portion (12) in the battery charger (10) as backup information, and restore processing in which the backup information stored in the storage portion (12) is transferred to the storage portion (3) as the personal information.

摘要翻译： 具有信息登记功能的便携式信息系统实现制造成本和功耗的降低。 通过连接便携式信息设备（1）和可充电的电池充电器（10），便携式信息设备（1）中的微控制器（2）和电池充电器（10）中的微控制器（11） 10）。 在微控制器（2,11）的控制下，充电期间自动执行信息管理操作。 操作包括备份处理，其中存储在便携式信息设备（1）中的存储部分（3）中的个人信息作为备份信息被传送到电池充电器（10）中的存储部分（12），并且其中恢复处理 存储在存储部分（12）中的备份信息作为个人信息被传送到存储部分（3）。

公开(公告)号：US6034563A

公开(公告)日：2000-03-07

申请号：US651588

申请日：1996-05-22

申请人： Koichiro Mashiko

发明人： Koichiro Mashiko

IPC分类号： H01L27/088 ,  G11C11/407 ,  H01L21/8234 ,  H01L27/02 ,  H03K17/16 ,  H03K19/00 ,  H03K19/0175 ,  H03K19/0948 ,  G05F1/10

CPC分类号： H03K19/0016 ,  H01L27/0218

摘要： A semiconductor integrated circuit including a first MOS transistor supplied with a first power supply voltage and having a high threshold voltage; a second MOS transistor supplied with a second power supply voltage and having the high threshold voltage; a logic circuit connected between the first transistor and the second transistor and including a plurality of MOS transistors having a low threshold voltage; a control circuit for generating a control signal when the logic circuit is in a standby state; and a voltage generating circuit for generating a first voltage which is a higher than the first power supply voltage and a second voltage which is a lower than the second power supply voltage, for supplying the first voltage to a gate of the first MOS transistor and for supplying the second voltage to a gate of the second MOS transistor when the logic circuit is in the standby state, thereby to decrease leakage current through the first and second transistors and through the logic circuit when in the standby state.

摘要翻译： 一种半导体集成电路，包括被提供有第一电源电压且具有高阈值电压的第一MOS晶体管; 提供有第二电源电压并具有高阈值电压的第二MOS晶体管; 连接在所述第一晶体管和所述第二晶体管之间并包括具有低阈值电压的多个MOS晶体管的逻辑电路; 控制电路，用于当所述逻辑电路处于待机状态时产生控制信号; 以及电压产生电路，用于产生比第一电源电压高的第一电压和低于第二电源电压的第二电压，用于将第一电压提供给第一MOS晶体管的栅极，并且为 当逻辑电路处于待机状态时，将第二电压提供给第二MOS晶体管的栅极，从而当处于待机状态时，通过第一和第二晶体管和逻辑电路减小漏电流。

公开(公告)号：US5475794A

公开(公告)日：1995-12-12

申请号：US292624

申请日：1994-08-17

申请人： Koichiro Mashiko

发明人： Koichiro Mashiko

IPC分类号： G06G7/60 ,  G06F15/18 ,  G06N3/04 ,  G06N3/063 ,  G06N99/00

CPC分类号： G06N3/063

摘要： A semiconductor neural network includes a coupling matrix having coupling elements arranged in a matrix which couple with specific coupling strengths internal data input lines to internal data output lines. The internal data output lines are divided into groups. The neural network further comprises weighting addition circuits provided corresponding to the groups of the internal data output lines. A weighting addition circuit includes weighing elements for adding weights to signals on the internal data output lines in the corresponding group and outputting the weighted signals, and an addition circuit for outputting a total sum of the outputs of those weighting elements. The internal data output lines are arranged to form pairs and the addition circuit has a first input terminal for receiving one weighting element output of each of the pairs in common, a second input terminal for receiving the other weighting element output of each of the pairs in common, and a sense amplifier for differentially amplifying signals at the first and second input terminals. The neural network further includes a circuit for detecting a change time of an input signal, a circuit responsive to an input signal change for equalizing the first and second input terminals for a predetermined period, and a circuit for activating the sense amplifier after the equalization is completed. The information retention capability of each coupling element is set according to the weight of an associated weighting element. This neural network can provide multi-valued expression of coupling strength with less number of coupling elements.

摘要翻译： 半导体神经网络包括耦合矩阵，其具有以矩阵布置的耦合元件，其耦合特定的耦合强度将内部数据输入线耦合到内部数据输出线。 内部数据输出线分为几组。 神经网络还包括对应于内部数据输出线的组提供的加权加法电路。 加权加法电路包括称重元件，用于对相应组中的内部数据输出线上的信号加权，并输出加权信号，以及加法电路，用于输出这些加权元件的输出的总和。 内部数据输出线被布置成形成对，并且加法电路具有用于共同地接收每对的一个加权元件输出的第一输入端子，用于接收每对中的每对的其他加权元件输出的第二输入端子 公共的，以及用于在第一和第二输入端子差分放大信号的读出放大器。 所述神经网络还包括用于检测输入信号的变化时间的电路，响应于用于使所述第一和第二输入端子均衡预定时间段的输入信号变化的电路，以及用于在均衡之后激活读出放大器的电路 完成 每个耦合元件的信息保持能力根据相关加权元件的权重来设置。 该神经网络可以提供耦合强度的多值表达式，较少数量的耦合元件。

公开(公告)号：US5293598A

公开(公告)日：1994-03-08

申请号：US912135

申请日：1992-07-09

申请人： Kiyohiro Furutani ,  Koichiro Mashiko ,  Kazutami Arimoto ,  Noriaki Matsumoto ,  Yoshio Matsuda

发明人： Kiyohiro Furutani ,  Koichiro Mashiko ,  Kazutami Arimoto ,  Noriaki Matsumoto ,  Yoshio Matsuda

IPC分类号： G06F11/267 ,  G11C7/10 ,  G11C29/26 ,  G11C29/38 ,  G06F13/40

CPC分类号： G11C7/10 ,  G11C29/26 ,  G11C29/38 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084 ,  G06F11/267

摘要： A semiconductor memory device operable for reading and writing in a normal mode and in a test mode is divided into memory cell sections each having blocks of memory cells. Data bus lines are connected to the respective blocks, and switches interconnect data bus lines connected to blocks of the different sections. The switch are made conductive during reading and writing in the normal mode and during writing in the test mode, and nonconductive during reading in the test mode. Input data are applied onto the data bus lines connected one of the blocks for writing in the blocks of the sections simultaneously during writing in the normal mode and in the test mode. In the normal mode, data are read out of the blocks of the sections through the data bus lines connected to the above-mentioned one of the blocks. In the test mode, the data are read out of the blocks of the sections through the data bus lines connected to the respective blocks.

摘要翻译： 可以以正常模式和测试模式读取和写入的半导体存储器件被分成具有存储单元块的存储单元部分。 数据总线连接到相应的块，并且交换连接到不同部分的块的数据总线。 在正常模式下读写时，在测试模式下写入期间开关导通，在测试模式下读取期间不导通。 在正常模式和测试模式下，输入数据被加到连接在一个块上的数据总线上，以便在写入期间同时在这些块中写入。 在正常模式下，通过连接到上述一个块的数据总线，从这些部分的块中读出数据。 在测试模式中，通过连接到相应块的数据总线，从这些部分的块中读出数据。

公开(公告)号：US5084746A

公开(公告)日：1992-01-28

申请号：US511909

申请日：1990-04-24

申请人： Kazutami Arimoto ,  Koichiro Mashiko ,  Kiyohiro Furutani

发明人： Kazutami Arimoto ,  Koichiro Mashiko ,  Kiyohiro Furutani

IPC分类号： H01L27/10 ,  G11C11/34 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10829

摘要： A semiconductor memory device having a folded bit line structure (16a, 16b), in which a field oxide film (2) is formed on both sides of a channel region (11) of a transfer gate, a groove isolation region 12 for defining a memory cell region is formed to surround the field oxide film 2, and the side walls of the groove isolation region 12 include a memory cell utilized as a capacitor for storing charges as information.

摘要翻译： 一种具有折叠的位线结构（16a，16b）的半导体存储器件，其中在转移栅极的沟道区域（11）的两侧形成有场氧化物膜（2），用于限定 存储单元区域形成为围绕场氧化物膜2，并且沟槽隔离区域12的侧壁包括用作用作电荷作为信息的电容器的存储单元。

公开(公告)号：US5021988A

公开(公告)日：1991-06-04

申请号：US410199

申请日：1989-09-21

申请人： Koichiro Mashiko

发明人： Koichiro Mashiko

IPC分类号： G06F15/18 ,  G06N3/06 ,  G06N3/063 ,  G06N99/00

CPC分类号： G06N3/0635

摘要： A semiconductor neural network includes a plurality of data input line pairs to which complementary input data pairs are transmitted respectively, data output line pairs respectively deriving complementary output data pairs and a plurality of coupling elements arranged at respective crosspoints of the data input lines and the data output lines. The coupling elements are programmable in states, and couple corresponding data output lines and corresponding data input lines in accordance with the programmed states thereof. Differential amplifiers formed by cross-coupled inverting amplifiers are provided in order to detect potentials on the data output lines. The differential amplifiers are provided for respective ones of the data output line pairs.

摘要翻译： 半导体神经网络包括分别发送互补输入数据对的多个数据输入线对，分别导出互补输出数据对的数据输出线对和排列在数据输入线和数据的各个交叉点的多个耦合元件 输出线。 耦合元件可以在状态下编程，并且根据其编程状态耦合相应的数据输出线和对应的数据输入线。 提供由交叉耦合反相放大器形成的差分放大器，以便检测数据输出线上的电位。 差分放大器为数据输出线对中的相应数据线提供。