公开(公告)号：US06797650B1

公开(公告)日：2004-09-28

申请号：US10342032

申请日：2003-01-14

申请人： Zhigang Wang ,  Nian Yang ,  John Jianshi Wang ,  Jiang Li

发明人： Zhigang Wang ,  Nian Yang ,  John Jianshi Wang ,  Jiang Li

IPC分类号： H01L2131

CPC分类号： H01L21/28202 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/3144 ,  H01L21/3145 ,  H01L29/513 ,  H01L29/518

摘要： One aspect of the invention relates to flash memory device that stores charge in a substantially stoichiometric silicon oxynitride dielectric. A stoichiometric silicon oxynitride dielectric can be represented by the formula (Si3N4)x(SiO2)(1-x), where x is from 0-1. A substantially stoichiometric silicon oxynitride dielectric has relatively few atoms that do not fit into the foregoing formula. The flash memory devices of the present invention have fewer defects and lower leakage than comparable SONOS-type flash memory devices. Another aspect of the invention relates to assessing the stoichiometry by FTIR, refractive index measurement, or a combination of the two.

摘要翻译： 本发明的一个方面涉及将电荷存储在基本上化学计量的氮氧化硅电介质中的闪存器件。 化学计量的氮氧化硅电介质可由式（Si 3 N 4）x（SiO 2）（1-x）表示，其中x为0-1。 基本上化学计量的氮氧化硅电介质具有不符合上述公式的相对较少的原子。 本发明的闪速存储器件具有比可比较的SONOS型闪存器件更少的缺陷和更低的泄漏。 本发明的另一方面涉及通过FTIR，折射率测量或两者的组合来评估化学计量。

公开(公告)号：US06734080B1

公开(公告)日：2004-05-11

申请号：US10159078

申请日：2002-05-31

申请人： Nian Yang ,  John Jianshi Wang ,  Tien-Chun Yang

发明人： Nian Yang ,  John Jianshi Wang ,  Tien-Chun Yang

IPC分类号： H01L2176

CPC分类号： H01L21/76229

摘要： A semiconductor isolation material deposition system and method that facilitates convenient and efficient integrated multi-step deposition of isolation regions is presented. In one embodiment of the present invention, an integrated circuit includes densely configured component areas and sparsely configured component areas. An active area in a wafer is created and a shallow trench space is formed. A thin layer of TEOS isolation material layer is deposited on top of the active area and the shallow trench. For example, the layer of thin layer of TEOS isolation material is in a range of 4000 to 5000 angstroms thick over the top of underlying active areas. A reverse mask and pre-planarization etch is performed on the thin layer of TEOS isolation material. The remaining TEOS edge spikes between the densely configured component area and the sparsely configured component area are minimal (e.g., about 500 angstroms. The remaining excess oxidant and silicon nitride are removed utilizing chemical mechanical polishing processes. In one exemplary implementation, the present invention facilitates an integrated approach to STI fabrication processes that achieve successful high yielding results by considering the impacts of one process step on another.

摘要翻译： 介绍了半导体隔离材料沉积系统及其方法，便于实现隔离区域的多步沉积。 在本发明的一个实施例中，集成电路包括密集配置的组件区域和稀疏配置的组件区域。 产生晶片中的有效区域并形成浅沟槽空间。 TEOS隔离材料层的薄层沉积在有源区域和浅沟槽的顶部。 例如，薄层的TEOS隔离材料层的厚度在下面有效区域顶部的4000至5000埃的范围内。 在TEOS隔离材料的薄层上进行反掩模和预平面化蚀刻。 在密集配置的部件区域和稀疏构造的部件区域之间的剩余的TEOS边缘尖峰是最小的（例如，约500埃），使用化学机械抛光工艺去除剩余的多余的氧化剂和氮化硅。在一个示例性实施方式中， 通过考虑一个工艺步骤对另一个工艺步骤的影响，可以获得成功的高产量结果的STI制造工艺的综合方法。

公开(公告)号：US06734028B1

公开(公告)日：2004-05-11

申请号：US10113152

申请日：2002-03-28

申请人： Tien-Chun Yang ,  Nian Yang ,  Hyeon-Seag Kim

发明人： Tien-Chun Yang ,  Nian Yang ,  Hyeon-Seag Kim

IPC分类号： H01L2166

CPC分类号： H01L22/34 ,  G01R31/275 ,  G01R31/2831

摘要： A method and apparatus for testing semiconductors comprising shallow trench isolation (STI) edge structures. An edge intensive shallow trench isolation structure (500) is coupled to a voltage source (310) and a current versus voltage profile is recorded. A planar structure (600) on the same wafer is coupled to a voltage source and a current versus voltage profile is recorded. An electrical stress is applied to both structures. Additional current profiles of each structure are obtained after the electrical stress. A comparison of difference current profiles obtained for the two types of structures may indicate the presence and/or the extent of STI corner effects. More specifically, a value for a normalized gate current difference for an STI edge intensive structure (500) greater than normalized gate current difference of a planar structure (600) is indicative of an increased rate of electron trapping in STI corners, which may indicate that the STI corners are too thin. In this novel manner, STI corner thickness may be observed in a non-destructive, electrical test process, resulting in higher quality and greater reliability of semiconductors using STI processes.

摘要翻译： 一种用于测试包括浅沟槽隔离（STI）边缘结构的半导体的方法和装置。 边缘密集的浅沟槽隔离结构（500）耦合到电压源（310），并记录电流对电压曲线。 在同一晶片上的平面结构（600）被耦合到电压源并且记录电流对电压曲线。 对两个结构都施加电应力。 在电应力之后，获得每个结构的附加电流分布。 对于两种类型的结构获得的差异电流曲线的比较可以指示STI拐角效应的存在和/或程度。 更具体地，大于平面结构（600）的归一化栅极电流差的STI边缘强化结构（500）的归一化栅极电流差的值表示STI拐角中的电子捕获速率增加，这可以指示 STI角落太薄了。 以这种新颖的方式，可以在非破坏性电气测试过程中观察到STI拐角厚度，从而导致使用STI工艺的半导体的更高质量和更高的可靠性。

公开(公告)号：US06646462B1

公开(公告)日：2003-11-11

申请号：US10178144

申请日：2002-06-24

申请人： Nian Yang ,  Zhigang Wang ,  Xin Guo

发明人： Nian Yang ,  Zhigang Wang ,  Xin Guo

IPC分类号： H01L2998

CPC分类号： H01L22/34 ,  H01L29/7836 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention generally relates to a method of determining a source/drain junction overlap and a channel length of a small device, such as a MOS transistor. A large reference device having a known channel length is provided, and a source, drain, and substrate on which the device has been formed are grounded. A predetermined gate voltage is applied to a gate of the large device, and a gate to channel current of the reference device is measured. A source, drain, and substrate on which the small device has been formed are grounded, and the predetermined voltage is applied to a gate of the small device, and a gate to channel current of the small device is measured. The substrate and one of the source or the drain of the small device is floated, and a predetermined drain voltage is applied to source or the drain which is not floating. A gate to drain current for the small device is measured, and a source/drain junction overlap length is calculated. The source/drain junction overlap length is then used to calculate the channel length of the small device.

摘要翻译： 本发明一般涉及一种确定诸如MOS晶体管的小器件的源/漏结重叠和沟道长度的方法。 提供具有已知通道长度的大参考装置，并且其上形成有装置的源极，漏极和基板接地。 将预定的栅极电压施加到大型器件的栅极，并测量参考器件的栅极到沟道电流。 形成小型器件的源极，漏极和衬底接地，并且将预定电压施加到小器件的栅极，并且测量小器件的栅极到沟道电流。 衬底和小器件的源极或漏极中的一个浮置，并且将预定的漏极电压施加到不浮动的源极或漏极。 测量用于小器件的漏极电流的栅极，并计算源极/漏极结重叠长度。 然后使用源极/漏极结重叠长度来计算小器件的沟道长度。

公开(公告)号：US06570787B1

公开(公告)日：2003-05-27

申请号：US10126330

申请日：2002-04-19

申请人： Zhigang Wang ,  Nian Yang ,  Xin Guo

发明人： Zhigang Wang ,  Nian Yang ,  Xin Guo

IPC分类号： G11C1604

CPC分类号： G11C16/12

摘要： The present invention relates to a flash memory array architecture comprising a plurality of flash memory cells arranged in a NOR type array configuration. Each of the plurality of flash memory cells have a source terminal coupled together to form a common source. The array architecture further comprises a common source selection component coupled between the common source of the array and a predetermined potential. The common source selection component is operable to couple the common source to the predetermined potential in a first state and electrically isolate or float the common source from the predetermined potential in a second state, thereby reducing leakage of non-selected cells associated with the activated bit line during a program mode of operation.

摘要翻译： 本发明涉及一种闪存阵列架构，其包括以NOR型阵列配置布置的多个闪存单元。 多个闪存单元中的每一个具有耦合在一起以形成公共源的源极端子。 阵列结构还包括耦合在阵列的公共源和预定电位之间的公共源选择部件。 公共源选择组件可操作以将公共源耦合到处于第一状态的预定电位，并且在第二状态下将公共源与预定电位电隔离或浮动，从而减少与激活位相关联的未选择单元的泄漏 在程序运行模式下运行。

公开(公告)号：US06472236B1

公开(公告)日：2002-10-29

申请号：US09904740

申请日：2001-07-13

申请人： Zhigang Wang ,  Nian Yang ,  Tien-Chun Yang

发明人： Zhigang Wang ,  Nian Yang ,  Tien-Chun Yang

IPC分类号： H01L2166

CPC分类号： H01L22/12

摘要： System and method for determining a respective effective oxide thickness for each of first and second dielectric structures that form a MOS (metal oxide semiconductor) stack. A first plurality of test MOS (metal oxide semiconductor) stacks are formed, and each test MOS stack includes a respective first dielectric structure comprised of a first dielectric material and a respective second dielectric structure comprised of a second dielectric material. A respective deposition time for forming the respective first dielectric structure corresponding to each of the first plurality of test MOS stacks is varied such that a respective first effective oxide thickness of the respective first dielectric structure varies for the first plurality of test MOS stacks. A respective second effective oxide thickness of the respective second dielectric structure is maintained to be substantially same for each of the first plurality of test MOS stacks. A respective total effective oxide thickness, EOTMOS, is measured for each of the first plurality of test MOS stacks. A first graph having total effective oxide thickness as a first axis and having deposition time for forming the first dielectric structure as a second axis is generated by plotting the respective total effective oxide thickness, EOTMOS, versus the respective deposition time for forming the respective first dielectric structure for each of the first plurality of test MOS stacks. The respective second effective oxide thickness of the respective second dielectric structure that is substantially same for each of the first plurality of test MOS stacks is determined from an intercept of the first axis of total effective oxide thickness when deposition time for forming the first dielectric structure of the second axis is substantially zero in the first graph.

摘要翻译： 用于确定形成MOS（金属氧化物半导体）堆叠的第一和第二电介质结构中的每一个的相应有效氧化物厚度的系统和方法。 形成第一多个测试MOS（金属氧化物半导体）堆叠，并且每个测试MOS堆叠包括由第一电介质材料和由第二电介质材料组成的相应的第二电介质结构的相应的第一电介质结构。 形成对应于第一多个测试MOS堆叠中的每一个的相应的第一介电结构的各自的沉积时间被改变，使得相应的第一介电结构的相应的第一有效氧化物厚度对于第一多个测试MOS堆叠而言是变化的。 相应的第二介电结构的相应的第二有效氧化物厚度被保持为对于第一多个测试MOS堆叠中的每一个基本相同。 对于第一多个测试MOS堆叠中的每一个测量相应的总有效氧化物厚度EOTMOS。 通过绘制相应的总有效氧化物厚度EOTMOS，相对于形成相应的第一电介质的相应沉积时间，产生具有总有效氧化物厚度作为第一轴并具有用于形成第一电介质结构作为第二轴的沉积时间的第一图 所述第一多个测试MOS堆叠中的每一个的结构。 对于第一多个测试MOS堆叠中的每一个基本上相同的相应的第二介电结构的相应的第二有效氧化物厚度是从形成第一介电结构的沉积时间的总有效氧化物厚度的第一轴的截距来确定的 在第一图中第二轴基本为零。

公开(公告)号：US07746706B2

公开(公告)日：2010-06-29

申请号：US11639935

申请日：2006-12-15

申请人： Nian Yang ,  Yonggang Wu ,  Tien-Chun Yang

发明人： Nian Yang ,  Yonggang Wu ,  Tien-Chun Yang

IPC分类号： G11C16/04

CPC分类号： G11C16/3404 ,  G11C16/0475

摘要： One embodiment of the invention relates to a method for accessing a memory cell. In this method, at least one bit of the memory cell is erased. After erasing the at least one bit, a soft program operation is performed to bias the memory cell thereby improving the reliability of data stored in the memory cell.Other methods and systems are also disclosed.

摘要翻译： 本发明的一个实施例涉及访问存储器单元的方法。 在该方法中，擦除存储单元的至少一位。 在擦除至少一个位之后，执行软编程操作以偏置存储器单元，从而提高存储在存储单元中的数据的可靠性。 还公开了其它方法和系统。

公开(公告)号：US07613044B2

公开(公告)日：2009-11-03

申请号：US11950811

申请日：2007-12-05

申请人： Nian Yang ,  Boon-Aik Ang ,  Yonggang Wu ,  Guowei Wang ,  Fan Wan Lai

发明人： Nian Yang ,  Boon-Aik Ang ,  Yonggang Wu ,  Guowei Wang ,  Fan Wan Lai

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/06 ,  G11C7/10

CPC分类号： G11C7/1039 ,  G11C8/08 ,  G11C16/0475 ,  G11C16/0491 ,  G11C16/08 ,  G11C16/30 ,  G11C2207/2245

摘要： A method and apparatus are provided for high performance, high voltage memory operations on selected memory cells (200) of a semiconductor memory device (100). A high voltage generator (106) during program or erase operations provides a continuous high voltage level (702) on selected word lines (502) and maintains a continuous high voltage level supply to a bit line decoder (120) which sequentially provides the high voltage level (706) to a first portion of bit lines (504) and discharges (708) those bit lines (504) before providing the high voltage level to a second portion (710). For additional improvements to program operations, the high voltage generator (106) decouples high voltages provided to the word lines (502) and the bit lines (504) by providing a current flow control device (1208) therebetween and provides a boosting voltage at a time (1104) to overcome a voltage level drop (1102) resulting from a capacitor load associated with selected bit lines (504) and/or the bit line decoder (120) precharges (1716) a second portion of the bit lines (504) while providing a high voltage level to a first portion to program (1706) a first portion of memory cells (200). For improvements to read operations, whether dynamic reference cells (2002) are blank is determined by providing non-identically regulated high voltage levels from a first voltage source (2112) to the dynamic reference cells (2002) and from a second voltage source (2104) to static reference cells (2004) and, if the dynamic reference cells (2002) are not blank, reads selected memory cells (200) by providing identically regulated high voltage levels to the selected memory cells (200), the dynamic reference cells (2002) and the static reference cells (2004).

摘要翻译： 提供了一种用于在半导体存储器件（100）的选定存储单元（200）上进行高性能，高电压存储器操作的方法和装置。 在编程或擦除操作期间，高电压发生器（106）在所选择的字线（502）上提供连续的高电压电平（702），并且向位线解码器（120）保持连续的高电压电平供应，位线解码器（120）依次提供高电压 电平（706）到位线（504）的第一部分，并且在将高电压电平提供给第二部分（710）之前对那些位线（504）进行放电（708）。 为了对编程操作进一步改进，高电压发生器（106）通过在其间提供电流控制装置（1208）来解耦提供给字线（502）和位线（504）的高电压，并在 时间（1104）以克服由与所选位线（504）和/或位线解码器（120）相关联的电容器负载导致的电压电平下降（1102），所述位线（504）的第二部分预充电（1716） 同时向第一部分提供高电压电平以对存储单元（200）的第一部分进行编程（1706）。 为了改进读取操作，动态参考单元（2002）是空白的是通过从第一电压源（2112）到动态参考单元（2002）和从第二电压源（2104）提供非相同调节的高电压电平来确定的 ）到静态参考单元（2004），并且如果动态参考单元（2002）不为空白，则通过向所选择的存储单元（200），动态参考单元（200）提供相同调节的高电压电平来读取所选存储单元（200） 2002）和静态参考单元（2004）。

公开(公告)号：US07532518B2

公开(公告)日：2009-05-12

申请号：US11767622

申请日：2007-06-25

申请人： Nian Yang ,  Fan Wan Lai ,  Aaron Lee

发明人： Nian Yang ,  Fan Wan Lai ,  Aaron Lee

IPC分类号： G11C16/06

CPC分类号： G11C16/30 ,  G11C16/10

摘要： Systems and methodologies are provided herein for increasing operation speed uniformity in a flash memory device. Due to the characteristics of a typical flash memory array, memory cells in a memory array may experience distributed substrate resistance that increases as the distance of the memory cell from an edge of the memory array increases. This difference in distributed substrate resistance can vary voltages supplied to different memory cells in the memory array depending on their location, which can in turn cause non-uniformity in the speed of high voltage operations on the memory array such as programming. The systems and methodologies provided herein reduce this non-uniformity in operation speed by providing compensated voltage levels to memory cells in a memory array based at least in part on the location of each respective memory cell. For example, a compensated operation voltage can be provided that is higher near the center of the memory array and lower near an edge of the memory array, thereby lessening the effect of distributed substrate resistance and providing increased operation speed uniformity throughout the memory array.

摘要翻译： 本文提供的系统和方法用于提高闪存设备中的操作速度均匀性。 由于典型的闪存阵列的特征，存储器阵列中的存储器单元可能经历分布式衬底电阻，随着存储器单元与存储器阵列的边缘的距离增加而增加。 分布式基板电阻的这种差异可以根据其位置改变提供给存储器阵列中的不同存储单元的电压，这进而导致存储器阵列上的高电压操作的速度（例如编程）的不一致。 本文提供的系统和方法通过至少部分地基于每个相应存储器单元的位置，通过向存储器阵列中的存储器单元提供补偿的电压电平来降低操作速度的不均匀性。 例如，可以提供补偿操作电压，其在存储器阵列的中心附近较高，并且在存储器阵列的边缘附近较低，从而减小分布式衬底电阻的影响并且提供整个存储器阵列中的增加的操作速度均匀性。

公开(公告)号：US20090119447A1

公开(公告)日：2009-05-07

申请号：US11935717

申请日：2007-11-06

申请人： Aaron Lee ,  Nian Yang ,  Jiani Zhang

发明人： Aaron Lee ,  Nian Yang ,  Jiani Zhang

IPC分类号： G06F12/00

CPC分类号： G11C16/0416 ,  G11C11/5635 ,  G11C16/16 ,  G11C16/24 ,  G11C16/3418 ,  G11C16/3427

摘要： Systems and/or methods that facilitate discharging bit lines (BL) associated with memory arrays in nonvolatile memory at a controlled rate are presented. A discharge component facilitates discharging the BL at a desired rate thus preventing the “hot switching” phenomenon from occurring within a y-decoder component(s) associated with the nonvolatile memory. The discharge component can be comprised of, in part, a discharge transistor component that controls the rate of BL discharge wherein the gate voltage of the discharge transistor component can be controlled by a discharge controller component. The rate of BL discharge can be determined by the size of discharge transistor component used in the design, the strength and/or size of the y-decoder component, the number of erase errors that occur for a particular memory device, and/or other factors in order to facilitate preventing hot switching from occurring.

摘要翻译： 提出了有助于以受控的速率放电与非易失性存储器中的存储器阵列相关联的位线（BL）的系统和/或方法。 放电元件有助于以期望的速率放电BL，从而防止在与非易失性存储器相关联的y解码器组件内发生“热切换”现象。 放电部件可以部分地由控制BL放电速率的放电晶体管部件组成，其中放电晶体管部件的栅极电压可以由放电控制器部件控制。 BL放电的速率可以由设计中使用的放电晶体管组件的大小，y解码器组件的强度和/或尺寸，特定存储器件发生的擦除错误的数量和/或其他 因素，以便于防止发生热切换。