公开(公告)号：US07224034B2

公开(公告)日：2007-05-29

申请号：US10978469

申请日：2004-11-02

申请人： Hiroshi Kujirai ,  Kousuke Okuyama ,  Kazuhiro Hata ,  Kiyonori Oyu ,  Ryo Nagai ,  Hiroyuki Uchiyama ,  Takahiro Kumauchi ,  Teruhisa Ichise

发明人： Hiroshi Kujirai ,  Kousuke Okuyama ,  Kazuhiro Hata ,  Kiyonori Oyu ,  Ryo Nagai ,  Hiroyuki Uchiyama ,  Takahiro Kumauchi ,  Teruhisa Ichise

IPC分类号： H01L29/76

CPC分类号： H01L29/4983 ,  H01L21/28061 ,  H01L21/28247 ,  H01L21/76897 ,  H01L27/10811 ,  H01L27/10814 ,  H01L27/10873 ,  H01L29/4941

摘要： Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET: Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.

摘要翻译： 公开了一种通过减少组成MISFET的多金属栅极的金属的污染来减少泄漏电流的技术：在p上的栅极绝缘膜上形成的多晶硅膜，WN膜，W膜和帽绝缘膜 （半导体衬底），帽绝缘膜，W膜和WN膜被蚀刻，并且进行其下面的多晶硅膜的过蚀刻。 然后，在这些膜的侧壁上形成侧壁膜。 此后，在以侧壁膜为掩模蚀刻多晶硅膜之后，在氧化气氛中进行热处理，在多晶硅膜的侧壁上形成有氧化膜。 结果，可以减少由W和W氧化物引起的栅绝缘膜上的污染，并且这些材料向半导体衬底（p型阱）的扩散以及由此导致的漏电流的增加 被阻止

公开(公告)号：US07190031B2

公开(公告)日：2007-03-13

申请号：US10629733

申请日：2003-07-30

申请人： Hiraku Chakihara ,  Kousuke Okuyama ,  Masahiro Moniwa ,  Makoto Mizuno ,  Keiji Okamoto ,  Mitsuhiro Noguchi ,  Tadanori Yoshida ,  Yasuhiko Takahshi ,  Akio Nishida

发明人： Hiraku Chakihara ,  Kousuke Okuyama ,  Masahiro Moniwa ,  Makoto Mizuno ,  Keiji Okamoto ,  Mitsuhiro Noguchi ,  Tadanori Yoshida ,  Yasuhiko Takahshi ,  Akio Nishida

IPC分类号： H01L29/78 ,  G11C11/412

CPC分类号： H01L29/6675 ,  H01L21/823885 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/7833 ,  H01L29/78642

摘要： Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with gate insulating films interposed therebetween. In each vertical MISFET, the lower semiconductor layer constitutes a drain, the intermediate semiconductor layer constitutes a substrate (channel region), and the upper semiconductor layer constitutes a source. The lower semiconductor layer, the intermediate semiconductor layer and the upper semiconductor layer are each comprised of a silicon film. The lower semiconductor layer and the upper semiconductor layer are doped with a p type and constituted of a p type silicon film.

摘要翻译： 垂直MISFET形成在驱动MISFET和传输MISFET上。 垂直MISFET包括通过层叠下半导体层（漏极），中间半导体层和上半导体层（源极）形成的矩形柱层叠体以及在层叠体的相应侧壁上形成有栅极绝缘膜的栅电极 插入其间。 在每个垂直MISFET中，下半导体层构成漏极，中间半导体层构成衬底（沟道区），上半导体层构成源极。 下半导体层，中间半导体层和上半导体层均由硅膜构成。 下半导体层和上半导体层掺杂有p型并由p型硅膜构成。

公开(公告)号：US20060208319A1

公开(公告)日：2006-09-21

申请号：US11418029

申请日：2006-05-05

申请人： Hiraku Chakihara ,  Kousuke Okuyama ,  Masahiro Moniwa ,  Makoto Mizuno ,  Keiji Okamoto ,  Mitsuhiro Noguchi ,  Tadanori Yoshida ,  Yasuhiko Takahshi ,  Akio Nishida

发明人： Hiraku Chakihara ,  Kousuke Okuyama ,  Masahiro Moniwa ,  Makoto Mizuno ,  Keiji Okamoto ,  Mitsuhiro Noguchi ,  Tadanori Yoshida ,  Yasuhiko Takahshi ,  Akio Nishida

IPC分类号： H01L29/94

CPC分类号： H01L29/6675 ,  H01L21/823885 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/7833 ,  H01L29/78642

摘要： Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with gate insulating films interposed therebetween. In each vertical MISFET, the lower semiconductor layer constitutes a drain, the intermediate semiconductor layer constitutes a substrate (channel region), and the upper semiconductor layer constitutes a source. The lower semiconductor layer, the intermediate semiconductor layer and the upper semiconductor layer are each comprised of a silicon film. The lower semiconductor layer and the upper semiconductor layer are doped with a p type and constituted of a p type silicon film.

摘要翻译： 垂直MISFET形成在驱动MISFET和传输MISFET上。 垂直MISFET包括通过层叠下半导体层（漏极），中间半导体层和上半导体层（源极）形成的矩形柱层叠体以及在层叠体的相应侧壁上形成有栅极绝缘膜的栅电极 插入其间。 在每个垂直MISFET中，下半导体层构成漏极，中间半导体层构成衬底（沟道区），上半导体层构成源极。 下半导体层，中间半导体层和上半导体层均由硅膜构成。 下半导体层和上半导体层掺杂有p型并由p型硅膜构成。

公开(公告)号：US20060202286A1

公开(公告)日：2006-09-14

申请号：US11418024

申请日：2006-05-05

申请人： Hiraku Chakihara ,  Kousuke Okuyama ,  Masahiro Moniwa ,  Makoto Mizuno ,  Keiji Okamoto ,  Mitsuhiro Noguchi ,  Tadanori Yoshida ,  Yasuhiko Takahshi ,  Akio Nishida

发明人： Hiraku Chakihara ,  Kousuke Okuyama ,  Masahiro Moniwa ,  Makoto Mizuno ,  Keiji Okamoto ,  Mitsuhiro Noguchi ,  Tadanori Yoshida ,  Yasuhiko Takahshi ,  Akio Nishida

IPC分类号： H01L29/76

CPC分类号： H01L29/6675 ,  H01L21/823885 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/7833 ,  H01L29/78642

摘要： Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with gate insulating films interposed therebetween. In each vertical MISFET, the lower semiconductor layer constitutes a drain, the intermediate semiconductor layer constitutes a substrate (channel region), and the upper semiconductor layer constitutes a source. The lower semiconductor layer, the intermediate semiconductor layer and the upper semiconductor layer are each comprised of a silicon film. The lower semiconductor layer and the upper semiconductor layer are doped with a p type and constituted of a p type silicon film.

公开(公告)号：US07098478B2

公开(公告)日：2006-08-29

申请号：US11168872

申请日：2005-06-29

申请人： Norikatsu Takaura ,  Hideyuki Matsuoka ,  Riichiro Takemura ,  Kousuke Okuyama ,  Masahiro Moniwa ,  Akio Nishida ,  Kota Funayama ,  Tomonori Sekiguchi

发明人： Norikatsu Takaura ,  Hideyuki Matsuoka ,  Riichiro Takemura ,  Kousuke Okuyama ,  Masahiro Moniwa ,  Akio Nishida ,  Kota Funayama ,  Tomonori Sekiguchi

IPC分类号： H01L29/72

CPC分类号： H01L27/11 ,  H01L27/0688 ,  H01L27/1104

摘要： The invention provides a semiconductor memory device comprising a plurality of word lines, a plurality of bit lines, and a plurality of static memory cells each having a first, second, third, fourth, fifth, and sixth transistors. While each of channels of the first, second, third, and fourth transistors are formed vertical against a substrate of the semiconductor memory device. Each of semiconductor regions forming a source or a drain of the fifth and sixth transistors forms a PN junction against the substrate. According to another aspect of the invention, the SRAM device of the invention has a plurality of SRAM cells, at least one of which is a vertical SRAM cell comprising at least four vertical transistors onto a substrate, and each vertical transistor includes a source, a drain, and a channel therebetween aligning in one aligning line which penetrates into the substrate surface at an angle greater than zero degree.

公开(公告)号：US06953728B2

公开(公告)日：2005-10-11

申请号：US10775236

申请日：2004-02-11

申请人： Eiichi Murakami ,  Akio Nishida ,  Kazunori Umeda ,  Kousuke Okuyama ,  Toshiaki Yamanaka ,  Jiro Yugami ,  Shinichiro Kimura

发明人： Eiichi Murakami ,  Akio Nishida ,  Kazunori Umeda ,  Kousuke Okuyama ,  Toshiaki Yamanaka ,  Jiro Yugami ,  Shinichiro Kimura

IPC分类号： H01L29/43 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L21/331 ,  H01L21/8222

CPC分类号： H01L27/10894 ,  H01L21/823412 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/10873

摘要： This semiconductor device manufacturing method comprises the steps of: forming a thick gate oxide film (thick oxide film) in a first region of a substrate, forming a thin gate oxide film (thin oxide layer) in a second region, and then, applying oxynitridation to these gate oxide films; forming gate electrodes to 1d on these gate oxide films; and implanting an ion that contains nitrogen or nitrogen atoms into at least one part of an interface between the hick gate oxide film (thick oxide film) and the substrate before or after the step of forming the gate electrodes, thereby forming a highly oxy-nitrided region. In this manner, in a semiconductor device in which there coexist a MISFET having a thin gate insulation film and a MISFET having a thick gate insulation film, hot carrier reliability of the MISFET having the thick gate insulation film is improved.

摘要翻译： 该半导体器件制造方法包括以下步骤：在衬底的第一区域形成厚栅氧化膜（厚氧化物膜），在第二区域形成薄的栅极氧化膜（薄氧化物层），然后施加氧氮化 到这些栅氧化膜; 在这些栅极氧化膜上形成栅电极至1d; 以及在形成栅电极的步骤之前或之后，将含有氮或氮原子的离子注入到所述堰栅氧化膜（厚氧化物膜）和所述衬底之间的界面的至少一部分中，从而形成高度氧氮化 地区。 以这种方式，在并入具有薄栅极绝缘膜的MISFET和具有厚栅极绝缘膜的MISFET的半导体器件中，具有厚栅极绝缘膜的MISFET的热载流子可靠性得到改善。

公开(公告)号：US06727146B2

公开(公告)日：2004-04-27

申请号：US10288448

申请日：2002-11-06

申请人： Eiichi Murakami ,  Akio Nishida ,  Kazunori Umeda ,  Kousuke Okuyama ,  Toshiaki Yamanaka ,  Jiro Yugami ,  Shinichiro Kimura

发明人： Eiichi Murakami ,  Akio Nishida ,  Kazunori Umeda ,  Kousuke Okuyama ,  Toshiaki Yamanaka ,  Jiro Yugami ,  Shinichiro Kimura

IPC分类号： H01L218234

CPC分类号： H01L27/10894 ,  H01L21/823412 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/10873

摘要： This semiconductor device manufacturing method comprises the steps of: forming a thick gate oxide film (thick oxide film) in a first region of a substrate, forming a thin gate oxide film (thin oxide layer) in a second region, and then, applying oxynitridation to these gate oxide films; forming gate electrodes to 1d on these gate oxide films; and implanting an ion that contains nitrogen or nitrogen atoms into at least one part of an interface between the hick gate oxide film (thick oxide film) and the substrate before or after the step of forming the gate electrodes, thereby forming a highly oxy-nitrided region. In this manner, in a semiconductor device in which there coexist a MISFET having a thin gate insulation film and a MISFET having a thick gate insulation film, hot carrier reliability of the MISFET having the thick gate insulation film is improved.

摘要翻译： 该半导体器件制造方法包括以下步骤：在衬底的第一区域形成厚栅氧化膜（厚氧化物膜），在第二区域形成薄的栅极氧化膜（薄氧化物层），然后施加氧氮化 到这些栅氧化膜; 在这些栅极氧化膜上形成栅电极至1d; 以及在形成栅电极的步骤之前或之后，将含有氮或氮原子的离子注入到所述堰栅氧化膜（厚氧化物膜）和所述衬底之间的界面的至少一部分中，从而形成高度氧氮化 地区。 以这种方式，在并入具有薄栅极绝缘膜的MISFET和具有厚栅极绝缘膜的MISFET的半导体器件中，具有厚栅极绝缘膜的MISFET的热载流子可靠性得到改善。

公开(公告)号：US06670642B2

公开(公告)日：2003-12-30

申请号：US10051188

申请日：2002-01-22

申请人： Norikatsu Takaura ,  Hideyuki Matsuoka ,  Riichiro Takemura ,  Kousuke Okuyama ,  Masahiro Moniwa ,  Akio Nishida ,  Kota Funayama ,  Tomonori Sekiguchi

发明人： Norikatsu Takaura ,  Hideyuki Matsuoka ,  Riichiro Takemura ,  Kousuke Okuyama ,  Masahiro Moniwa ,  Akio Nishida ,  Kota Funayama ,  Tomonori Sekiguchi

IPC分类号： H01L2972

CPC分类号： H01L27/11 ,  H01L27/0688 ,  H01L27/1104

摘要： The invention provides a semiconductor memory device comprising a plurality of word lines, a plurality of bit lines, and a plurality of static memory cells each having a first, second, third, fourth, fifth, and sixth transistors. While each of channels of the first, second, third, and fourth transistors are formed vertical against a substrate of the semiconductor memory device. Each of semiconductor regions forming a source or a drain of the fifth and sixth transistors forms a PN junction against the substrate. According to another aspect of the invention, the SRAM device of the invention has a plurality of SRAM cells, at least one of which is a vertical SRAM cell comprising at least four vertical transistors onto a substrate, and each vertical transistor includes a source, a drain, and a channel therebetween aligning in one aligning line which penetrates into the substrate surface at an angle greater than zero degree.

公开(公告)号：US5063170A

公开(公告)日：1991-11-05

申请号：US460011

申请日：1990-01-02

申请人： Kousuke Okuyama

发明人： Kousuke Okuyama

IPC分类号： H01L21/8246 ,  H01L27/112

CPC分类号： H01L27/1126 ,  H01L27/112

摘要： A semiconductor integrated circuit device having a read-only memory which comprises a plurality of first gate electrodes arranged on a semiconductor substrate in a first direction maintaining a predetermined distance, a plurality of second gate electrodes that are arranged among said first gate electrodes and are partly overlapped on said first gate electrodes, and regions of data-writing impurities positioned under the first and second gate electrodes. The impurities for writing data are introduced through the first or second gate electrodes using the overlappings of the first and second gate electrodes as masks.

公开(公告)号：US08576634B2

公开(公告)日：2013-11-05

申请号：US12764090

申请日：2010-04-20

申请人： Fumitoshi Ito ,  Yoshiyuki Kawashima ,  Takeshi Sakai ,  Yasushi Ishii ,  Yasuhiro Kanamaru ,  Takashi Hashimoto ,  Makoto Mizuno ,  Kousuke Okuyama ,  Yukiko Manabe

发明人： Fumitoshi Ito ,  Yoshiyuki Kawashima ,  Takeshi Sakai ,  Yasushi Ishii ,  Yasuhiro Kanamaru ,  Takashi Hashimoto ,  Makoto Mizuno ,  Kousuke Okuyama ,  Yukiko Manabe

IPC分类号： G11C11/34 ,  H01L29/792

CPC分类号： H01L27/11568 ,  G11C16/0466 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792

摘要： The degree of integration and the number of rewriting of a semiconductor device having a nonvolatile memory element are improved. A first MONOS nonvolatile-memory-element and a second MONOS nonvolatile-memory-element having a large gate width compared with the first MONOS nonvolatile-memory-element are mounted together on the same substrate, and the first MONOS nonvolatile-memory-element is used for storing program data which is scarcely rewritten, and the second MONOS nonvolatile-memory-element is used for storing processed data which is frequently rewritten.

摘要翻译： 改善了具有非易失性存储元件的半导体器件的积分度和重写次数。 与第一MONOS非易失性存储元件相比，具有大门宽度的第一MONOS非易失性存储元件和第二MONOS非易失性存储元件一起安装在同一衬底上，并且第一MONOS非易失性存储元件是 用于存储几乎不被重写的程序数据，并且第二MONOS非易失性存储元件用于存储频繁重写的处理数据。