公开(公告)号：US20100118616A1

公开(公告)日：2010-05-13

申请号：US12591176

申请日：2009-11-12

申请人： Hoe-Ju Chung ,  Ki-Whan Song

发明人： Hoe-Ju Chung ,  Ki-Whan Song

IPC分类号： G11C7/10 ,  G11C7/00 ,  G11C8/10

CPC分类号： G11C7/06 ,  G11C7/1012 ,  G11C7/12 ,  G11C7/18 ,  G11C2207/005

摘要： A semiconductor memory device having shared sense amplifiers is provided. The semiconductor memory device has a bit-line selector disposed closer to a memory cell array than a column decoder. When the column decoder outputs a bit-line indication signal corresponding to the number of bit lines, the bit-line selector selects a plurality of bit lines in response to the bit-line indication signal. Thus, it is possible to reduce the number of signals output from the column decoder.

摘要翻译： 提供了具有共享读出放大器的半导体存储器件。 半导体存储器件具有比列解码器更靠近存储单元阵列设置的位线选择器。 当列解码器输出与位线数相对应的位线指示信号时，位线选择器响应于位线指示信号选择多个位线。 因此，可以减少从列解码器输出的信号的数量。

公开(公告)号：US07596043B2

公开(公告)日：2009-09-29

申请号：US12327201

申请日：2008-12-03

申请人： Jae-Jun Lee ,  Hoe-Ju Chung

发明人： Jae-Jun Lee ,  Hoe-Ju Chung

IPC分类号： G11C7/00

CPC分类号： H03L7/0812

摘要： A delay locked loop (DLL) circuit for a synchronous semiconductor memory device which can control a delay time of a feedback loop within the DLL circuit according to the magnitude of an external load, and a method of generating information about a load connected to a data pin of a synchronous semiconductor memory device are provided. The DLL circuit includes a replica output driver delaying an internal clock signal by a first delay time to output a first internal clock signal, the first delay time is a delay time of the internal clock signal which is generated by an output driver when a first load of a first magnitude is connected to an output terminal of the output driver, and a transfer/delay circuit transferring the first delay internal clock signal to a phase detector as a second delay internal clock signal when the first load is connected to the output terminal, and outputting the second delay internal clock signal to the phase detector by delaying the first delay internal clock signal by a second delay time, the second delay time is a delay time of the internal clock signal which is generated by the output driver when a second load of a second magnitude, which is larger than the first magnitude, is connected to the output terminal.

公开(公告)号：US20090080272A1

公开(公告)日：2009-03-26

申请号：US12327201

申请日：2008-12-03

申请人： JAE-JUN LEE ,  Hoe-Ju Chung

发明人： JAE-JUN LEE ,  Hoe-Ju Chung

IPC分类号： G11C7/00

CPC分类号： H03L7/0812

摘要： A delay locked loop (DLL) circuit for a synchronous semiconductor memory device which can control a delay time of a feedback loop within the DLL circuit according to the magnitude of an external load, and a method of generating information about a load connected to a data pin of a synchronous semiconductor memory device are provided. The DLL circuit includes a replica output driver delaying an internal clock signal by a first delay time to output a first internal clock signal, the first delay time is a delay time of the internal clock signal which is generated by an output driver when a first load of a first magnitude is connected to an output terminal of the output driver, and a transfer/delay circuit transferring the first delay internal clock signal to a phase detector as a second delay internal clock signal when the first load is connected to the output terminal, and outputting the second delay internal clock signal to the phase detector by delaying the first delay internal clock signal by a second delay time, the second delay time is a delay time of the internal clock signal which is generated by the output driver when a second load of a second magnitude, which is larger than the first magnitude, is connected to the output terminal.

摘要翻译： 用于同步半导体存储器件的延迟锁定环（DLL）电路，其可以根据外部负载的大小来控制DLL电路内的反馈回路的延迟时间，以及生成关于连接到数据的负载的信息的方法 提供同步半导体存储器件的引脚。 DLL电路包括复制输出驱动器，延迟第一延迟时间的内部时钟信号以输出第一内部时钟信号，第一延迟时间是当输出驱动器第一次加载时产生的内部时钟信号的延迟时间 第一幅度的第一延迟连接到输出驱动器的输出端，以及传输/延迟电路，当第一负载连接到输出端时，将第一延迟内部时钟信号传送到相位检测器作为第二延迟内部时钟信号， 并且通过将所述第一延迟内部时钟信号延迟第二延迟时间，将所述第二延迟内部时钟信号输出到所述相位检测器，所述第二延迟时间是由所述输出驱动器产生的内部时钟信号的延迟时间， 大于第一幅度的第二幅度连接到输出端。

公开(公告)号：US07380152B2

公开(公告)日：2008-05-27

申请号：US11165340

申请日：2005-06-24

申请人： Hoe-Ju Chung

发明人： Hoe-Ju Chung

IPC分类号： G06F1/00

CPC分类号： G11C5/04 ,  G11C29/02 ,  G11C29/50012

摘要： A multi-device system having a daisy chain system bus structure and related method of operation are disclosed. A reference signal having a defined oscillation period is communicated around the daisy chain bus structure. Total signal transmission time around the daisy chain bus structure as well as signal transmission time to each one of a plurality of client devices connected to a host device by the daisy chain bus structure may be readily determined.

摘要翻译： 公开了一种具有菊花链系统总线结构和相关操作方法的多器件系统。 具有限定的振荡周期的参考信号围绕菊花链总线结构传送。 可以容易地确定围绕菊花链总线结构的总信号传输时间以及通过菊花链总线结构连接到主机设备的多个客户端设备中的每一个的信号传输时间。

公开(公告)号：US20080080285A1

公开(公告)日：2008-04-03

申请号：US11730275

申请日：2007-03-30

申请人： Jung Sunwoo ,  Yun-Sang Lee ,  Hoe-Ju Chung

发明人： Jung Sunwoo ,  Yun-Sang Lee ,  Hoe-Ju Chung

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C11/40618

摘要： A refresh method for a semiconductor memory device having more than one bank group is provided. The refresh method may include applying an all-refresh command to one the bank groups, determining if one of the bank groups includes a bank undergoing a refresh operation when the all-refresh command is received, and performing an all-refresh operation based on the determination.

摘要翻译： 提供了具有多于一个组组的半导体存储器件的刷新方法。 刷新方法可以包括：将全刷新命令应用于银行组中的一个，当接收到全刷新命令时，确定银行组中的一个是否包括经历刷新操作的存储体，并且基于所述刷新操作执行全刷新操作 决心。

公开(公告)号：US20070286011A1

公开(公告)日：2007-12-13

申请号：US11783509

申请日：2007-04-10

申请人： Hoe-Ju Chung

发明人： Hoe-Ju Chung

IPC分类号： G11C8/16

CPC分类号： G11C8/16 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084 ,  G11C8/18 ,  G11C2207/107

摘要： A memory device is adapted to be connected in a daisy chain with a memory controller and one or more other memory devices. The memory device includes at least one data input port and at least one data output port for communicating data along the daisy-chain between the memory devices and the memory controller. The memory device is adapted to selectively enable/disable at least one of the data input or data output ports in response to whether a command received from the memory controller is intended for the memory device, or for one of the other memory devices.

摘要翻译： 存储器装置适于以菊花链与存储器控制器和一个或多个其它存储器件连接。 存储器件包括至少一个数据输入端口和至少一个数据输出端口，用于沿存储器件和存储器控制器之间的菊花链传送数据。 响应于从存储器控制器接收到的命令是针对存储器设备还是其他存储器件之一，存储器件适于选择性地启用/禁用数据输入端口或数据输出端口中的至少一个。

公开(公告)号：US20070156996A1

公开(公告)日：2007-07-05

申请号：US11646553

申请日：2006-12-28

申请人： Hoe-Ju Chung

发明人： Hoe-Ju Chung

IPC分类号： G06F13/28

CPC分类号： G06F13/1689

摘要： A memory system may include a memory device and a memory controller. The memory device may include a first bank and a second bank. The memory controller may include a read request scheduling queue that may store a read request, and may controls the read request scheduling queue so that if first and the second read requests to the first bank and a third read request to the second bank occur successively, data from the memory device may be output seamlessly by applying a first additive latency to first and second read requests to the first bank, and by applying a second additive latency to a third read request to the second bank.

摘要翻译： 存储器系统可以包括存储器设备和存储器控制器。 存储器件可以包括第一存储体和第二存储体。 存储器控制器可以包括可以存储读请求的读请求调度队列，并且可以控制读请求调度队列，使得如果对第一存储体的第一和第二读请求以及到第二存储体的第三读请求连续发生， 通过对第一存储体应用第一和第二读取请求的第一附加等待时间，并且通过对第二存储体应用第三附加延迟到第三读取请求，可以无缝地输出来自存储器装置的数据。

公开(公告)号：US20050053120A1

公开(公告)日：2005-03-10

申请号：US10837391

申请日：2004-04-29

申请人： Kyu-Hyoun Kim ,  Hoe-Ju Chung

发明人： Kyu-Hyoun Kim ,  Hoe-Ju Chung

IPC分类号： H03K5/1252 ,  G06F1/08 ,  H03K5/00 ,  H03K5/13 ,  H03K5/156 ,  H04B1/69 ,  H04B15/02

CPC分类号： H04B15/02 ,  G06F1/08 ,  H03K5/133 ,  H03K5/156 ,  H03K2005/00071 ,  H04B2215/067

摘要： A spread spectrum clock generator includes a non-volatile memory to store control codes corresponding to a predetermined delay. A delay circuit receives a control code having a predetermined number of bits that determine a delay to apply to a fixed clock signal a period of time. The delay mitigates the electromagnetic interference caused by a periodic clock signal.

摘要翻译： 扩频时钟发生器包括用于存储对应于预定延迟的控制码的非易失性存储器。 延迟电路在一段时间内接收具有确定延迟的预定位数的控制码，以应用于固定时钟信号。 该延迟减轻了周期性时钟信号引起的电磁干扰。