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    Method of detecting error in a semiconductor memory device
    1.
    发明申请
    Method of detecting error in a semiconductor memory device 有权
    检测半导体存储器件中的误差的方法

    公开(公告)号：US20110107191A1

    公开(公告)日：2011-05-05

    申请号：US12929250

    申请日：2011-01-11

    申请人： Hoe-Ju Chung ,  Kyu-Hyoun Kim

    发明人： Hoe-Ju Chung ,  Kyu-Hyoun Kim

    IPC分类号： H03M13/09 ,  G06F11/10

    CPC分类号： H03M13/29 ,  G06F11/08 ,  G06F11/1008 ,  G11C7/1006 ,  G11C29/42 ,  G11C2029/0411 ,  G11C2207/104

    摘要： A semiconductor memory device and a memory system including the same are provided. The semiconductor memory device may include a first memory cell array block generating first data, a second memory cell array block generating second data, and first and second error detection code generators. The first error detection code generator may generate a first error detection code and may combine a portion of bits of the first error detection code with a portion of bits of a second error detection code to generate a first final error detection signal. The second error detection code generator may generate the second error detection code and may combine the remaining bits other than the portion of bits of the second error detection code with the remaining bits other than the portion of bits of the first error detection code to generate a second final error detection signal.

    摘要翻译： 提供一种半导体存储器件和包括该半导体存储器件的存储器系统。 半导体存储器件可以包括产生第一数据的第一存储单元阵列块，产生第二数据的第二存储单元阵列块，以及第一和第二错误检测码发生器。 第一错误检测码发生器可以产生第一错误检测码，并且可以将第一错误检测码的位的一部分与第二错误检测码的位的一部分组合以产生第一最终错误检测信号。 第二错误检测码发生器可以产生第二错误检测码，并且可以将除了第二错误检测码的位的部分之外的其余位与除第一错误检测码的位的部分之外的其余位组合以产生 第二最终错误检测信号。

    Semiconductor memory device having duty cycle correction circuit and interpolation circuit interpolating clock signal in the semiconductor memory device
    2.
    发明授权
    Semiconductor memory device having duty cycle correction circuit and interpolation circuit interpolating clock signal in the semiconductor memory device 有权
    在半导体存储器件中具有占空比校正电路和内插电路内插时钟信号的半导体存储器件

    公开(公告)号：US06934215B2

    公开(公告)日：2005-08-23

    申请号：US10656303

    申请日：2003-09-04

    申请人： Hoe-Ju Chung ,  Kyu-Hyoun Kim

    发明人： Hoe-Ju Chung ,  Kyu-Hyoun Kim

    IPC分类号： G06F1/04 ,  G06F1/10 ,  G11C7/22 ,  G11C11/40 ,  G11C11/407 ,  H03K5/05 ,  H03K5/156 ,  G11C8/00

    CPC分类号： H03K5/1565 ,  G11C7/22 ,  G11C7/222

    摘要： A semiconductor memory device having a duty cycle correction circuit and an interpolating circuit interpolating a clock signal in the semiconductor memory device are disclosed. The semiconductor memory device comprises a duty cycle correction circuit, which receives an external clock, corrects the duty cycle of the external clock, and outputs the corrected duty cycle. The duty cycle correction circuit comprises a first delay locked loop that receives the external clock, inverts the external clock, synchronizes the external clock with the inverted external clock, and outputs the synchronized clock; a second delay locked loop that receives the inverted external clock, synchronizes the inverted external clock with the external clock and outputs the synchronized clock; an inverting circuit that inverts the output signal of the first delay locked loop; an interpolation circuit that interpolates the output signal of the inverting circuit with the output signal of the second delay locked loop, and outputs the interpolated signal; and a control circuit that controls the interpolation circuit in response to the clock frequency information of the external clock.

    摘要翻译： 公开了一种具有占空比校正电路和内插半导体存储器件中的时钟信号的内插电路的半导体存储器件。 半导体存储器件包括占空比校正电路，其接收外部时钟，校正外部时钟的占空比，并输出校正的占空比。 占空比校正电路包括接收外部时钟的第一延迟锁定环，反相外部时钟，使外部时钟与反相外部时钟同步，并输出同步时钟; 接收反相外部时钟的第二个延迟锁定环，将反相外部时钟与外部时钟同步并输出同步时钟; 反相电路，其使所述第一延迟锁定环路的输出信号反相; 内插电路，用第二延迟锁定环的输出信号内插反相电路的输出信号，并输出内插信号; 以及控制电路，其响应于外部时钟的时钟频率信息来控制内插电路。

    Semiconductor memory device and memory system including the same
    3.
    发明授权
    Semiconductor memory device and memory system including the same 有权
    半导体存储器件和包括其的存储器系统

    公开(公告)号：US07882417B2

    公开(公告)日：2011-02-01

    申请号：US11705151

    申请日：2007-02-12

    申请人： Hoe-Ju Chung ,  Kyu-Hyoun Kim

    发明人： Hoe-Ju Chung ,  Kyu-Hyoun Kim

    IPC分类号： G11C29/00 ,  H03M13/29

    CPC分类号： H03M13/29 ,  G06F11/08 ,  G06F11/1008 ,  G11C7/1006 ,  G11C29/42 ,  G11C2029/0411 ,  G11C2207/104

    摘要： A semiconductor memory device and a memory system including the same are provided. The semiconductor memory device may include a first memory cell array block generating first data, a second memory cell array block generating second data, and first and second error detection code generators. The first error detection code generator may generate a first error detection code and may combine a portion of bits of the first error detection code with a portion of bits of a second error detection code to generate a first final error detection signal. The second error detection code generator may generate the second error detection code and may combine the remaining bits other than the portion of bits of the second error detection code with the remaining bits other than the portion of bits of the first error detection code to generate a second final error detection signal.

    摘要翻译： 提供一种半导体存储器件和包括该半导体存储器件的存储器系统。 半导体存储器件可以包括产生第一数据的第一存储单元阵列块，产生第二数据的第二存储单元阵列块，以及第一和第二错误检测码发生器。 第一错误检测码发生器可以产生第一错误检测码，并且可以将第一错误检测码的位的一部分与第二错误检测码的位的一部分组合以产生第一最终错误检测信号。 第二错误检测码发生器可以产生第二错误检测码，并且可以将除了第二错误检测码的位的部分之外的其余位与除第一错误检测码的位的部分之外的其余位组合以产生 第二最终错误检测信号。

    Spread spectrum clock generator
    4.
    发明授权
    Spread spectrum clock generator 失效
    扩频时钟发生器

    公开(公告)号：US07573932B2

    公开(公告)日：2009-08-11

    申请号：US10837391

    申请日：2004-04-29

    申请人： Kyu-Hyoun Kim ,  Hoe-Ju Chung

    发明人： Kyu-Hyoun Kim ,  Hoe-Ju Chung

    IPC分类号： H04B1/00

    CPC分类号： H04B15/02 ,  G06F1/08 ,  H03K5/133 ,  H03K5/156 ,  H03K2005/00071 ,  H04B2215/067

    摘要： A spread spectrum clock generator includes a non-volatile memory to store control codes corresponding to a predetermined delay. A delay circuit receives a control code having a predetermined number of bits that determine a delay to apply to a fixed clock signal a period of time. The delay mitigates the electromagnetic interference caused by a periodic clock signal.

    摘要翻译： 扩频时钟发生器包括用于存储对应于预定延迟的控制码的非易失性存储器。 延迟电路在一段时间内接收具有确定延迟的预定位数的控制码，以应用于固定时钟信号。 该延迟减轻了周期性时钟信号引起的电磁干扰。

    Semiconductor memory device and memory system including the same
    5.
    发明申请
    Semiconductor memory device and memory system including the same 有权
    半导体存储器件和包括其的存储器系统

    公开(公告)号：US20070204199A1

    公开(公告)日：2007-08-30

    申请号：US11705151

    申请日：2007-02-12

    申请人： Hoe-Ju Chung ,  Kyu-Hyoun Kim

    发明人： Hoe-Ju Chung ,  Kyu-Hyoun Kim

    IPC分类号： G11C29/00

    CPC分类号： H03M13/29 ,  G06F11/08 ,  G06F11/1008 ,  G11C7/1006 ,  G11C29/42 ,  G11C2029/0411 ,  G11C2207/104

    摘要： A semiconductor memory device and a memory system including the same are provided. The semiconductor memory device may include a first memory cell array block generating first data, a second memory cell array block generating second data, and first and second error detection code generators. The first error detection code generator may generate a first error detection code and may combine a portion of bits of the first error detection code with a portion of bits of a second error detection code to generate a first final error detection signal. The second error detection code generator may generate the second error detection code and may combine the remaining bits other than the portion of bits of the second error detection code with the remaining bits other than the portion of bits of the first error detection code to generate a second final error detection signal.

    摘要翻译： 提供一种半导体存储器件和包括该半导体存储器件的存储器系统。 半导体存储器件可以包括产生第一数据的第一存储单元阵列块，产生第二数据的第二存储单元阵列块，以及第一和第二错误检测码发生器。 第一错误检测码发生器可以产生第一错误检测码，并且可以将第一错误检测码的位的一部分与第二错误检测码的位的一部分组合以产生第一最终错误检测信号。 第二错误检测码发生器可以产生第二错误检测码，并且可以将除了第二错误检测码的位的部分之外的其余位与除第一错误检测码的位的部分之外的其余位组合以产生 第二最终错误检测信号。

    Semiconductor device and method of outputting data therein
    6.
    发明授权
    Semiconductor device and method of outputting data therein 失效

    公开(公告)号：US06590421B2

    公开(公告)日：2003-07-08

    申请号：US10101475

    申请日：2002-03-19

    申请人： Hoe-Ju Chung ,  Kyu-Hyoun Kim ,  Il-Won Seo ,  Moo-Sung Chae

    发明人： Hoe-Ju Chung ,  Kyu-Hyoun Kim ,  Il-Won Seo ,  Moo-Sung Chae

    IPC分类号： H03K190175

    CPC分类号： H03K19/00323

    摘要： A semiconductor capable of reducing skew between plural-bit output data by using a plurality of data output drivers and a method thereof. Each data output driver comprises a driver connected between an external power voltage and an external ground voltage, for pulling-up the output data in response to a first state of input data and for pulling-down the output data in response to a second state of the input data; a first delay circuit for varying transition delay time of the input data having the first state in response to signals received from other data output drivers; and a second delay circuit for varying transition delay time of the input data having the second state in response to signals received from other data output drivers.

    Method of detecting error in a semiconductor memory device
    7.
    发明授权
    Method of detecting error in a semiconductor memory device 有权
    检测半导体存储器件中的误差的方法

    公开(公告)号：US08756475B2

    公开(公告)日：2014-06-17

    申请号：US12929250

    申请日：2011-01-11

    申请人： Hoe-Ju Chung ,  Kyu-Hyoun Kim

    发明人： Hoe-Ju Chung ,  Kyu-Hyoun Kim

    IPC分类号： H03M13/00 ,  H03M13/29 ,  G06F11/08

    CPC分类号： H03M13/29 ,  G06F11/08 ,  G06F11/1008 ,  G11C7/1006 ,  G11C29/42 ,  G11C2029/0411 ,  G11C2207/104

    摘要： A semiconductor memory device and a memory system including the same are provided. The semiconductor memory device may include a first memory cell array block generating first data, a second memory cell array block generating second data, and first and second error detection code generators. The first error detection code generator may generate a first error detection code and may combine a portion of bits of the first error detection code with a portion of bits of a second error detection code to generate a first final error detection signal. The second error detection code generator may generate the second error detection code and may combine the remaining bits other than the portion of bits of the second error detection code with the remaining bits other than the portion of bits of the first error detection code to generate a second final error detection signal.

    摘要翻译： 提供一种半导体存储器件和包括该半导体存储器件的存储器系统。 半导体存储器件可以包括产生第一数据的第一存储单元阵列块，产生第二数据的第二存储单元阵列块，以及第一和第二错误检测码发生器。 第一错误检测码发生器可以产生第一错误检测码，并且可以将第一错误检测码的位的一部分与第二错误检测码的位的一部分组合以产生第一最终错误检测信号。 第二错误检测码发生器可以产生第二错误检测码，并且可以将除了第二错误检测码的位的部分之外的其余位与除第一错误检测码的位的部分之外的其余位组合以产生 第二最终错误检测信号。

    Latency control circuit and method using queuing design method
    10.
    发明授权
    Latency control circuit and method using queuing design method 失效
    延迟控制电路和使用排队设计方法的方法

    公开(公告)号：US08230140B2

    公开(公告)日：2012-07-24

    申请号：US13178846

    申请日：2011-07-08

    申请人： Byung-Hoon Jeong ,  Hoe-Ju Chung

    发明人： Byung-Hoon Jeong ,  Hoe-Ju Chung

    IPC分类号： G06F3/00

    CPC分类号： G11C7/22 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/109 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/4093 ,  G11C2207/2272

    摘要： A latency control circuit includes a FIFO controller and a register unit. The FIFO controller may generate an increase signal according to an external command, and generate a decrease signal according to an internal command. The FIFO controller may also enable a depth point signal responsive to the increase signal and the decrease signal. The register unit may include n registers. The value n (rounded off) may be obtained by dividing a larger value of a maximum number of additive latencies and a maximum number of write latencies by a column cycle delay time (tCCD). The registers may store an address received with the external command responsive to the increase signal and a clock signal, and may shift either the address or a previous address to a neighboring register. The latency control circuit transmits an address stored in a register as a column address corresponding to the enabled depth point signal.

    摘要翻译： 等待时间控制电路包括FIFO控制器和寄存器单元。 FIFO控制器可以根据外部命令生成增加信号，并根据内部命令生成减少信号。 FIFO控制器还可以响应于增加信号和减小信号启用深度点信号。 寄存器单元可以包括n个寄存器。 值n（四舍五入）可以通过将最大数量的加性延迟和最大写入延迟数的较大值除以列周期延迟时间（tCCD）来获得。 寄存器可以响应于增加信号和时钟信号而存储与外部命令接收的地址，并且可以将地址或先前地址移位到相邻寄存器。 延迟控制电路将存储在寄存器中的地址作为与启用的深度点信号相对应的列地址。