公开(公告)号：US06885587B2

公开(公告)日：2005-04-26

申请号：US10604798

申请日：2003-08-18

申请人： Ching-Sung Yang ,  Shih-Jye Shen ,  Ching-Hsiang Hsu

发明人： Ching-Sung Yang ,  Shih-Jye Shen ,  Ching-Hsiang Hsu

IPC分类号： G11C16/04

CPC分类号： H01L27/11521 ,  G11C16/0408 ,  G11C16/0433 ,  G11C2216/10 ,  H01L27/11558

摘要： A novel structure of nonvolatile memory is disclosed. The non-volatile memory includes two serially connected PMOS transistors. The characteristic of the devices is that bias is not necessary to apply to the floating gate during the programming mode. Thus, the control gate is omitted for the structure or layout, thereby saving the space for making the control gate. The carrier may be “automatically injected” into floating gate for programming the status of the devices.

摘要翻译： 公开了一种非易失性存储器的新颖结构。 非易失性存储器包括两个串联连接的PMOS晶体管。 器件的特性是在编程模式期间，偏置不需要应用于浮动栅极。 因此，对于结构或布局省略了控制栅，从而节省了用于制造控制栅的空间。 载体可以“自动注入”到浮动栅极中，用于对装置的状态进行编程。

公开(公告)号：US06847087B2

公开(公告)日：2005-01-25

申请号：US10065591

申请日：2002-10-31

申请人： Ching-Sung Yang ,  Shih-Jye Shen ,  Ching-Hsiang Hsu

发明人： Ching-Sung Yang ,  Shih-Jye Shen ,  Ching-Hsiang Hsu

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L27/11521 ,  G11C16/0433 ,  G11C16/0483 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/7883

摘要： A low-voltage nonvolatile memory array includes a cell well of a first conductivity type formed in a substrate; columns of buried bit lines of a second conductivity type formed within the cell well, wherein columns of the buried bit lines are isolated from each other and each is further divided into of sub-bit line segments with deeply doped source wells of the first conductivity type connected to the cell well; a plurality of memory cell blocks serially arranged over one of the columns of buried bit lines, wherein a memory cell block corresponds to a sub-bit line segment, and each memory cell block includes at least one memory transistor having a stacked gate, source, and drain; and a local bit line overlying the memory cell blocks and electrically connected to the drain of the memory transistor via a contact plug short-circuiting the drain and the subjacent buried bit line.

摘要翻译： 低压非易失性存储器阵列包括形成在衬底中的第一导电类型的电池阱; 在单元阱内形成的第二导电类型的掩埋位线的列，其中掩埋位线的列彼此隔离，并且每个被划分为具有第一导电类型的深掺杂源阱的子位线段 连接细胞很好; 多个存储单元块，串行布置在一列掩埋位线之上，其中存储单元块对应于子位线段，并且每个存储单元块包括至少一个具有堆叠栅极，源极， 排水 以及覆盖存储器单元块的局部位线，并且通过使漏极和下埋置位线短路的接触插头电连接到存储晶体管的漏极。

公开(公告)号：US06819594B2

公开(公告)日：2004-11-16

申请号：US10248282

申请日：2003-01-06

申请人： Kung-Hong Lee ,  Ching-Hsiang Hsu ,  Ya-Chin King ,  Shih-Jye Shen ,  Ming-Chiu Ho

发明人： Kung-Hong Lee ,  Ching-Hsiang Hsu ,  Ya-Chin King ,  Shih-Jye Shen ,  Ming-Chiu Ho

IPC分类号： G11C1604

CPC分类号： G11C16/0408 ,  G11C2216/10 ,  H01L27/115 ,  H01L27/118

摘要： An electrically erasable programmable logic device includes a P-type substrate, a first N-type doped region located inside the P-type substrate, and a first gate located on the P-type substrate. The first gate is adjacent to the first N-type doped region, is in a floating state, and is used for storing data. A second N-type doped region is located inside the P-type substrate adjacent to the first gate. A second gate is located on the P-type substrate and adjacent to the second N-type doped region and acts as a select gate. A third N-type doped region is located inside the P-type substrate adjacent to the second gate.

公开(公告)号：US06740556B1

公开(公告)日：2004-05-25

申请号：US10249075

申请日：2003-03-14

申请人： Ching-Hsiang Hsu ,  Chih-Hsun Chu ,  Ming-Chou Ho ,  Shih-Jye Shen

发明人： Ching-Hsiang Hsu ,  Chih-Hsun Chu ,  Ming-Chou Ho ,  Shih-Jye Shen

IPC分类号： H01L218247

CPC分类号： H01L27/11521 ,  G11C16/0408 ,  G11C2216/10 ,  H01L27/115 ,  H01L27/11558

摘要： A method for forming an electrically programmable read-only memory(EPROM) includes forming a first p+ doped region, a second p+ doped region, and a third p+ doped region on an N-well, forming a control gate between the first p+ doped region and the second p+ doped region, and forming a p+ floating gate between the second p+ doped region and the third p+ doped region.

摘要翻译： 一种用于形成电可编程只读存储器（EPROM）的方法包括在N阱上形成第一p +掺杂区，第二p +掺杂区和第三p +掺杂区，形成 在第一p +掺杂区和第二p +掺杂区之间的控制栅极，以及在第二p +掺杂区和第三p +掺杂区之间形成p + +浮置栅。

公开(公告)号：US06617637B1

公开(公告)日：2003-09-09

申请号：US10065718

申请日：2002-11-13

申请人： Ching-Hsiang Hsu ,  Yen-Tai Lin ,  Chih-Hsun Chu ,  Shih-Jye Shen ,  Ching-Sung Yang ,  Ming-Chou Ho

发明人： Ching-Hsiang Hsu ,  Yen-Tai Lin ,  Chih-Hsun Chu ,  Shih-Jye Shen ,  Ching-Sung Yang ,  Ming-Chou Ho

IPC分类号： H01L2976

CPC分类号： H01L27/115 ,  G11C2216/10 ,  H01L29/42324 ,  H01L29/7885

摘要： An electrically erasable programmable logic device (EEPLD) includes a P type semiconductor substrate. An N type well is formed on the P type semiconductor substrate. A first PMOS transistor is formed on the N well. The first PMOS transistor comprises a floating gate, a first P+ doped region serving as a drain of the first PMOS transistor, and a P− doped region encompassing an N+ doped region for erasing the first PMOS transistor. A second PMOS transistor is also formed on the N well and serially connected to the first PMOS transistor. The first P+ doped region functions as a source of the second PMOS transistor, and the second PMOS transistor further comprises a select gate and a second P+ doped region serving as a drain of the second PMOS transistor.

摘要翻译： 电可擦除可编程逻辑器件（EEPLD）包括P型半导体衬底。 在P型半导体衬底上形成N型阱。 在N阱上形成第一PMOS晶体管。 第一PMOS晶体管包括浮置栅极，用作第一PMOS晶体管的漏极的第一P +掺杂区域和包围用于擦除第一PMOS晶体管的N +掺杂区域的P-掺杂区域。 第二PMOS晶体管也形成在N阱上并串联连接到第一PMOS晶体管。 第一P +掺杂区域用作第二PMOS晶体管的源极，并且第二PMOS晶体管还包括用作第二PMOS晶体管的漏极的选择栅极和第二P +掺杂区域。

公开(公告)号：US08646152B2

公开(公告)日：2014-02-11

申请号：US13110233

申请日：2011-05-18

申请人： Zheng-Cheng Lin ,  Ching-Hsiang Hsu

发明人： Zheng-Cheng Lin ,  Ching-Hsiang Hsu

IPC分类号： E05D11/10

CPC分类号： E05F1/1207 ,  E05D3/04 ,  E05Y2201/638 ,  E05Y2900/606 ,  F16H25/186

摘要： A transversely movable hinge is mounted between a base and a cover of a folding device and has a moving assembly. The moving assembly is connected to an expansion device via a linking rod. Therefore, when the folding device is opened, the expansion device is driven to extend and is convenient for users. When the folding device is closed, the expansion device is driven to retract for saving space.

摘要翻译： 横向可移动的铰链安装在折叠装置的底座和盖子之间并具有移动组件。 移动组件通过连接杆连接到膨胀装置。 因此，当折叠装置打开时，扩展装置被驱动延伸并且方便用户。 当折叠装置关闭时，扩展装置被驱动缩回以节省空间。

公开(公告)号：US20120292201A1

公开(公告)日：2012-11-22

申请号：US13457970

申请日：2012-04-27

申请人： Ching-Hsiang Hsu

发明人： Ching-Hsiang Hsu

IPC分类号： C09K13/00 ,  C09K13/02 ,  C25F5/00 ,  C09K13/10

CPC分类号： C25F5/00 ,  C22B11/042 ,  C25F3/02 ,  C25F3/22 ,  Y02P10/214 ,  Y02W30/54

摘要： The invention provides a stripping gold component which could remove gold from substrate, comprising: a stripping gold chemical compound; and a assistant conductive compound wherein said stripping gold chemical compound bonds with gold to form covalent bond to strip gold from said substrate, said assistant conductive chemical compound helps the electric conduction and decreases the voltage, said substrate would not be damaged after stripping gold from said substrate, and the stripping gold component is cyanide free.

摘要翻译： 本发明提供了一种剥离金成分，其可从基底上除去金，其包括：剥离金化合物; 和辅助导电化合物，其中所述剥离金化合物与金键合以形成共价键以从所述基底剥离金，所述辅助导电化合物有助于导电并降低电压，所述基底在从所述基底剥离金后不会被损坏 底物，剥离金成分不含氰化物。

公开(公告)号：US07655782B2

公开(公告)日：2010-02-02

申请号：US11778934

申请日：2007-07-17

申请人： Ching-Hsiang Hsu ,  Wei-Chih Su

发明人： Ching-Hsiang Hsu ,  Wei-Chih Su

IPC分类号： C07H21/02 ,  C07H21/04

CPC分类号： A61K39/35 ,  C07H21/04 ,  C07K14/43531 ,  Y10S530/868

摘要： The present invention provides a modified Dermatophagoides pteronyssinus allergen Der p 5 protein which has ability to inhibit IgE binding when exposed against to the antigen. A method for treating allergy comprising administrating a therapeutically effective dose of the modified D. pteronyssinus allergen Der p 5 protein to a subject suffering from allergy Der p 5 is also provided.

摘要翻译： 本发明提供了当暴露于抗原时具有抑制IgE结合的能力的修饰的Dermatophagoides pteronyssinus变应原Der p 5蛋白。 还提供了治疗过敏的方法，其包括将治疗有效剂量的经修饰的D.tteronyssinus变应原Der p 5蛋白施用于患有过敏Der p 5的受试者。

公开(公告)号：US20080297497A1

公开(公告)日：2008-12-04

申请号：US11756878

申请日：2007-06-01

申请人： Ling-Chih Lu ,  Ching-Hsiang Hsu

发明人： Ling-Chih Lu ,  Ching-Hsiang Hsu

IPC分类号： G09G5/00

CPC分类号： G09G3/3648 ,  G09G2320/0252 ,  G09G2320/041 ,  G09G2340/16

摘要： A control circuit of a liquid crystal display (LCD) panel and a method thereof are provided. The circuit includes a frame memory, a look-up table (LUT) module, and a signal processor. The frame memory provides a previous value of a pixel, and the previous value includes at least one bit of a previous frame data of the pixel. The LUT module provides a plurality of basic values according to the previous value and a current value of the pixel, and the current value includes at least one bit of a current frame data of the pixel. The signal processor produces a driving value according to the basic values and replaces the current frame data with the driving value.

摘要翻译： 提供液晶显示（LCD）面板的控制电路及其方法。 电路包括帧存储器，查找表（LUT）模块和信号处理器。 帧存储器提供像素的先前值，并且先前值包括像素的先前帧数据的至少一个比特。 LUT模块根据先前的值和像素的当前值提供多个基本值，并且当前值包括像素的当前帧数据的至少一个比特。 信号处理器根据基本值产生驱动值，并用驱动值代替当前帧数据。

公开(公告)号：US07272387B2

公开(公告)日：2007-09-18

申请号：US10714626

申请日：2003-11-18

申请人： Ching-Hsiang Hsu ,  Charlie C. Chen ,  Hsiao-Wei Hsu ,  Kan-Lin Lee

发明人： Ching-Hsiang Hsu ,  Charlie C. Chen ,  Hsiao-Wei Hsu ,  Kan-Lin Lee

IPC分类号： H04Q7/22

CPC分类号： H04W16/00 ,  H04W4/04 ,  H04W4/20 ,  H04W8/06 ,  H04W64/00 ,  H04W84/02 ,  H04W84/10

摘要： An island type mobile communication arrangement is disclosed. A plurality of BTSs connected to BSCs are reassigned as island BTSs and connected to an island BSC, the island BSC is connected to an island MSC. When entering or leaving the scope of the island MSC, a cellular phone performs a location updating procedure, and thus the island type mobile communication arrangement can provide a special service to all cellular phones in a particular local area by reading MSISDNs in an island VLR corresponding to the island MSC.

摘要翻译： 公开了一种岛式移动通信装置。 连接到BSC的多个BTS被重新分配为岛BTS并连接到岛BSC，岛BSC连接到岛MSC。 当进入或离开岛MSC的范围时，蜂窝电话执行位置更新过程，因此岛式移动通信装置可以通过读取对应的岛屿VLR中的MSISDN来向特定局部区域中的所有蜂窝电话提供特殊服务 到海岛MSC。