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    Integrated circuit embedded with single-poly non-volatile memory
    1.
    发明授权
    Integrated circuit embedded with single-poly non-volatile memory 有权
    集成电路嵌入单聚合非易失性存储器

    公开(公告)号：US06920067B2

    公开(公告)日：2005-07-19

    申请号：US10248193

    申请日：2002-12-25

    申请人： Ching-Hsiang Hsu ,  Chih-Hsun Chu ,  Ming-Chou Ho ,  Shih-Jye Shen

    发明人： Ching-Hsiang Hsu ,  Chih-Hsun Chu ,  Ming-Chou Ho ,  Shih-Jye Shen

    IPC分类号： H01L21/8247 ,  G11C16/04 ,  H01L27/115 ,  H01L27/118 ,  H01L29/788 ,  H01L29/792

    CPC分类号： G11C16/0408 ,  G11C2216/10 ,  H01L27/115 ,  H01L27/118

    摘要： A system on chip (SOC) contains a core circuit and an input/output (I/O) circuit embedded with an array of single-poly erasable programmable read only memory cells, each of which comprises a first PMOS transistor serially connected to a second PMOS transistor. The first and second PMOS transistors are both formed on an N-well of a P-type substrate. The first PMOS transistor includes a single-poly floating gate, a first P+ doped drain region and a first P+ doped source region, the second PMOS transistor includes a single-poly select gate and a second P+ doped source region, and the first P+ doped source region of the first PMOS transistor serves as a drain of the second PMOS transistor.

    摘要翻译： 芯片上系统（SOC）包含一个内核电路和一个嵌入单个多可擦除可编程只读存储器单元的阵列的输入/输出（I / O）电路，每个存储单元包括串联连接到第二个 PMOS晶体管。 第一和第二PMOS晶体管都形成在P型衬底的N阱上。 第一PMOS晶体管包括单多晶硅浮置栅极，第一P + SUP掺杂漏极区域和第一P + +掺杂源极区域，第二PMOS晶体管包括： 多选择栅极和第二P + +掺杂源极区域，并且第一PMOS晶体管的第一P + +掺杂源极区域用作第二PMOS晶体管的漏极。

    Electrically erasable programmable logic device
    3.
    发明授权
    Electrically erasable programmable logic device 失效
    电可擦除可编程逻辑器件

    公开(公告)号：US06617637B1

    公开(公告)日：2003-09-09

    申请号：US10065718

    申请日：2002-11-13

    申请人： Ching-Hsiang Hsu ,  Yen-Tai Lin ,  Chih-Hsun Chu ,  Shih-Jye Shen ,  Ching-Sung Yang ,  Ming-Chou Ho

    发明人： Ching-Hsiang Hsu ,  Yen-Tai Lin ,  Chih-Hsun Chu ,  Shih-Jye Shen ,  Ching-Sung Yang ,  Ming-Chou Ho

    IPC分类号： H01L2976

    CPC分类号： H01L27/115 ,  G11C2216/10 ,  H01L29/42324 ,  H01L29/7885

    摘要： An electrically erasable programmable logic device (EEPLD) includes a P type semiconductor substrate. An N type well is formed on the P type semiconductor substrate. A first PMOS transistor is formed on the N well. The first PMOS transistor comprises a floating gate, a first P+ doped region serving as a drain of the first PMOS transistor, and a P− doped region encompassing an N+ doped region for erasing the first PMOS transistor. A second PMOS transistor is also formed on the N well and serially connected to the first PMOS transistor. The first P+ doped region functions as a source of the second PMOS transistor, and the second PMOS transistor further comprises a select gate and a second P+ doped region serving as a drain of the second PMOS transistor.

    摘要翻译： 电可擦除可编程逻辑器件（EEPLD）包括P型半导体衬底。 在P型半导体衬底上形成N型阱。 在N阱上形成第一PMOS晶体管。 第一PMOS晶体管包括浮置栅极，用作第一PMOS晶体管的漏极的第一P +掺杂区域和包围用于擦除第一PMOS晶体管的N +掺杂区域的P-掺杂区域。 第二PMOS晶体管也形成在N阱上并串联连接到第一PMOS晶体管。 第一P +掺杂区域用作第二PMOS晶体管的源极，并且第二PMOS晶体管还包括用作第二PMOS晶体管的漏极的选择栅极和第二P +掺杂区域。

    Method for operating a NAND-array memory module composed of P-type memory cells
    4.
    发明授权
    Method for operating a NAND-array memory module composed of P-type memory cells 有权
    用于操作由P型存储单元组成的NAND阵列存储模块的方法

    公开(公告)号：US06952369B2

    公开(公告)日：2005-10-04

    申请号：US10707562

    申请日：2003-12-22

    申请人： Ching-Hsiang Hsu ,  Ching-Sung Yang ,  Jih-Wen Chou ,  Cheng-Tung Huang ,  Chih-Hsun Chu

    发明人： Ching-Hsiang Hsu ,  Ching-Sung Yang ,  Jih-Wen Chou ,  Cheng-Tung Huang ,  Chih-Hsun Chu

    IPC分类号： G11C16/02 ,  G11C11/34 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC分类号： G11C16/0475

    摘要： A method for writing a memory module includes providing a plurality of memory cells, applying a first transmission line voltage to the first transmission line of the column of a memory cell, turning on a P-type channel of a memory cell between the memory cell to be written and the first transmission line of the column of the memory cell, turning off the P-type channel of at least one memory cell between the memory cell and the second transmission line of the column of the memory cell, applying a word line voltage to a word line connected to the memory cell, in order to inject hot electrons on a junction between the substrate and the first P-type doped region of the memory cell into a silicon nitride layer of the memory cell using band-to-band tunneling injection, and applying a substrate voltage to the substrates of the plurality of memory cells.

    摘要翻译： 一种用于写入存储器模块的方法包括提供多个存储器单元，将第一传输线电压施加到存储器单元的列的第一传输线，将存储单元之间的存储单元的P型通道导通到 写入存储单元的列的第一传输线，关闭存储单元和存储单元的列的第二传输线之间的至少一个存储单元的P型通道，施加字线电压 连接到连接到存储器单元的字线，以便使用带 - 带隧穿将热电子注入存储器单元的第一P型掺杂区域中的结，成为存储单元的氮化硅层 注入，并且将衬底电压施加到多个存储单元的衬底。

    METHOD FOR OPERATING A NAND-ARRAY MEMORY MODULE COMPOSED OF P-TYPE MEMORY CELLS
    5.
    发明申请
    METHOD FOR OPERATING A NAND-ARRAY MEMORY MODULE COMPOSED OF P-TYPE MEMORY CELLS 有权
    用于操作由P型存储器单元组成的NAND阵列存储器模块的方法

    公开(公告)号：US20050030789A1

    公开(公告)日：2005-02-10

    申请号：US10707562

    申请日：2003-12-22

    申请人： Ching-Hsiang Hsu ,  Ching-Sung Yang ,  Jih-Wen Chou ,  Cheng-Tung Huang ,  Chih-Hsun Chu

    发明人： Ching-Hsiang Hsu ,  Ching-Sung Yang ,  Jih-Wen Chou ,  Cheng-Tung Huang ,  Chih-Hsun Chu

    IPC分类号： G11C16/02 ,  G11C11/34 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC分类号： G11C16/0475

    摘要： A method for writing a memory module includes providing a plurality of memory cells, applying a first transmission line voltage to the first transmission line of the column of a memory cell, turning on a P-type channel of a memory cell between the memory cell to be written and the first transmission line of the column of the memory cell, turning off the P-type channel of at least one memory cell between the memory cell and the second transmission line of the column of the memory cell, applying a word line voltage to a word line connected to the memory cell, in order to inject hot electrons on a junction between the substrate and the first P-type doped region of the memory cell into a silicon nitride layer of the memory cell using band-to-band tunneling injection, and applying a substrate voltage to the substrates of the plurality of memory cells.

    摘要翻译： 一种用于写入存储器模块的方法包括提供多个存储器单元，将第一传输线电压施加到存储器单元的列的第一传输线，将存储单元之间的存储单元的P型通道导通到 写入存储单元的列的第一传输线，关闭存储单元和存储单元的列的第二传输线之间的至少一个存储单元的P型通道，施加字线电压 连接到连接到存储器单元的字线，以便使用带 - 带隧穿将热电子注入存储器单元的第一P型掺杂区域中的结，成为存储单元的氮化硅层 注入，并且将衬底电压施加到多个存储单元的衬底。

    Method for programming, erasing and reading a flash memory cell
    6.
    发明授权
    Method for programming, erasing and reading a flash memory cell 有权
    编程，擦除和读取闪存单元的方法

    公开(公告)号：US06801456B1

    公开(公告)日：2004-10-05

    申请号：US10707474

    申请日：2003-12-17

    申请人： Ching-Hsiang Hsu ,  Chih-Hsun Chu ,  Jih-Wen Chou ,  Cheng-Tung Huang

    发明人： Ching-Hsiang Hsu ,  Chih-Hsun Chu ,  Jih-Wen Chou ,  Cheng-Tung Huang

    IPC分类号： G11C1604

    CPC分类号： G11C16/10 ,  G11C16/0466

    摘要： A method for programming PMOS single transistor flash memory cells through channel hot carrier induced hot electron injection mechanism is disclosed. The PMOS single transistor flash memory cell includes an ONO stack layer situated on an N-well of a semiconductor substrate, a P+ poly gate formed on the ONO stack layer, a P+ doped source region disposed in the N-well at one side of the gate, and a P+ doped drain region disposed in the N-well at the other side of the gate. The method includes the steps of: applying a word line voltage VWL on the P+ poly gate, applying a source line voltage VSL on the source, wherein the source line voltage VSL is greater than the word line voltage VWL, thereby providing adequate bias to turn on the P channel thereof. A bit line voltage that is smaller than the source line voltage VSL is applied on the P+ doped drain region, thereby driving channel hot holes to flow toward the P+ doped drain region and then inducing hot electron injection near the drain side. A well voltage VNW is applied to the N-well, wherein VNW=VSL.

    摘要翻译： 公开了一种通过通道热载流子诱发的热电子注入机制来编程PMOS单晶体管闪存单元的方法。 PMOS单晶体管闪存单元包括位于半导体衬底的N阱上的ONO堆叠层，形成在ONO堆叠层上的P +多晶硅栅极，设置在N + 并且在栅极的另一侧设置在N阱中的P +掺杂漏极区。 该方法包括以下步骤：在P ++多栅极上施加字线电压VWL，在源极上施加源极线电压VSL，其中源极线电压VSL大于字线电压VWL，从而提供足够的 偏置以打开其P通道。 小于源极线电压VSL的位线电压施加在P +掺杂漏极区域上，从而驱动通道热孔流向P +掺杂漏极区域，然后在漏极附近引入热电子注入 侧。 将井电压VNW施加到N阱，其中VNW = VSL。

    Micro-trench oxidation by using rough oxide mask for field isolation
    8.
    发明授权
    Micro-trench oxidation by using rough oxide mask for field isolation 失效
    通过使用粗氧化物掩模进行微沟槽氧化，进行现场隔离

    公开(公告)号：US6008106A

    公开(公告)日：1999-12-28

    申请号：US915693

    申请日：1997-08-21

    申请人： Tuby Tu ,  Chen Kuang-Chao ,  Cheng-Tsung Ni ,  Chih-Hsun Chu

    发明人： Tuby Tu ,  Chen Kuang-Chao ,  Cheng-Tsung Ni ,  Chih-Hsun Chu

    IPC分类号： H01L21/308 ,  H01L21/762 ,  H01L21/76

    CPC分类号： H01L21/3081 ,  H01L21/7621

    摘要： A method of forming isolation region of an integrated circuit by using rough oxide mask is described. First, a layer of first dielectric is formed on the surface of a silicon substrate. The first dielectric layer is then patterned to define active device region and isolation region. Next, a very thin layer of silicon dioxide is formed over the silicon substrate surface, followed by depositing a layer of rough oxide with proper grain size overlaying the silicon dioxide layer. By using rough oxide grains as an etching mask, the silicon dioxide layer and the silicon substrate underneath are spontaneously etched to form multiple trenches in the isolation region. Next, the rough oxide grains and silicon dioxide layers are stripped. Then, filed oxidation is performed to complete the field oxide isolation formation.

    摘要翻译： 描述了通过使用粗略氧化物掩膜形成集成电路的隔离区域的方法。 首先，在硅衬底的表面上形成第一电介质层。 然后将第一介电层图案化以限定有源器件区域和隔离区域。 接下来，在硅衬底表面上形成非常薄的二氧化硅层，随后沉积具有覆盖二氧化硅层的适当晶粒尺寸的粗大氧化物层。 通过使用粗糙氧化物晶粒作为蚀刻掩模，自发蚀刻下面的二氧化硅层和硅衬底，以在隔离区域中形成多个沟槽。 接下来，剥离粗糙的氧化物颗粒和二氧化硅层。 然后进行归档氧化以完成场氧化物隔离层。

    Process for fabricating MOS device having short channel
    9.
    发明授权
    Process for fabricating MOS device having short channel 失效
    制造具有短通道的MOS器件的工艺

    公开(公告)号：US5926712A

    公开(公告)日：1999-07-20

    申请号：US753216

    申请日：1996-11-21

    申请人： Min-Liang Chen ,  Chih-Hsien Wang ,  Chih-Hsun Chu ,  San-Jung Chang

    发明人： Min-Liang Chen ,  Chih-Hsien Wang ,  Chih-Hsun Chu ,  San-Jung Chang

    IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L29/10

    CPC分类号： H01L29/66537 ,  H01L29/1083 ,  H01L29/6659 ,  H01L21/26586

    摘要： The present invention is related to a process for fabricating a MOS device having a short channel. The process according to the present invention includes the steps of (a) providing a semiconductor substrate and forming a gate structure on the semiconductor substrate; (b) implanting impurities of a first charge type to the semiconductor substrate with the gate structure serving as a mask to form a first source/drain region having a predetermined impurity concentration; (c) pocket-implanting impurities of a second charge type to the resulting semiconductor substrate with the gate structure serving as a mask to form a second source/drain region having a predetermined impurity concentration; and (d) forming a gate side wall on a flank of the gate structure, and implanting impurities of the first charge type to the resulting semiconductor substrate with the gate structure and the gate side wall serving as a mask to form a third source/drain region having a predetermined impurity concentration. The present invention is characterized in that no threshold voltage adjustment implantation to the semiconductor substrate is needed prior to the growth of the gate structure, and in stead, the diffusion ability of the pocket-implanted impurities in the step (c) can concurrently adjust the threshold voltage of the device.

    摘要翻译： 本发明涉及制造具有短通道的MOS器件的工艺。 根据本发明的方法包括以下步骤：（a）提供半导体衬底并在半导体衬底上形成栅极结构; （b）以栅极结构作为掩模将半导体衬底中的第一种类型的杂质注入到半导体衬底中，形成具有预定杂质浓度的第一源/漏区; （c）以所述栅极结构作为掩模将所述第二电荷型杂质注入所得的半导体衬底，以形成具有预定杂质浓度的第二源/漏区; 以及（d）在所述栅极结构的侧面上形成栅极侧壁，并且以所述栅极结构和所述栅极侧壁用作掩模，将所述第一电荷类型的杂质注入所得半导体衬底，以形成第三源极/漏极 区域具有预定的杂质浓度。 本发明的特征在于，在栅极结构生长之前，不需要对半导体衬底进行阈值电压调整注入，而是步骤（c）中的注入袋的杂质的扩散能力可以同时调节 器件的阈值电压。

    Semicondutor device and manufacturing method thereof
    10.
    发明授权
    Semicondutor device and manufacturing method thereof 有权
    半导体器件及其制造方法

    公开(公告)号：US07462545B2

    公开(公告)日：2008-12-09

    申请号：US11162727

    申请日：2005-09-21

    申请人： Jih-Wen Chou ,  Chih-Hsun Chu

    发明人： Jih-Wen Chou ,  Chih-Hsun Chu

    IPC分类号： H01L21/336

    CPC分类号： H01L29/0653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636

    摘要： A semiconductor device is provided. The semiconductor device has a gate structure, a source region, a drain region, and a pair of dielectric barrier layers. The gate structure is formed on a substrate. The source region and the drain region are formed in the substrate next to the gate structure, and a channel region is formed between the source region and the drain region underneath the gate structure. The pair of dielectric barrier layers is respectively formed in the substrate underneath the gate structure between the source region and the drain region. The dielectric barrier layers are used for reducing the drain induced barrier lowering effect in a nanometer scale device.

    摘要翻译： 提供半导体器件。 半导体器件具有栅极结构，源极区，漏极区和一对介电阻挡层。 栅极结构形成在基板上。 源极区域和漏极区域形成在栅极结构旁边的衬底中，并且在栅极结构之下的源极区域和漏极区域之间形成沟道区域。 一对电介质阻挡层分别形成在源极区域和漏极区域之间的栅极结构下方的衬底中。 电介质阻挡层用于在纳米级装置中降低漏极引发的阻挡层降低效果。