公开(公告)号：US20120009741A1

公开(公告)日：2012-01-12

申请号：US13131126

申请日：2010-09-07

申请人： Jing Chen ,  Qingqing Wu ,  Jiexin Luo ,  Xiaolu Huang ,  Xi Wang

发明人： Jing Chen ,  Qingqing Wu ,  Jiexin Luo ,  Xiaolu Huang ,  Xi Wang

IPC分类号： H01L21/336

CPC分类号： H01L29/458 ,  H01L29/66772 ,  H01L29/78615 ,  H01L29/78621

摘要： The present invention discloses a manufacturing method of SOI MOS device having a source/body ohmic contact. The manufacturing method comprises steps of: firstly creating a gate region, then performing high dose source and drain light doping to form the lightly doped N-type source region and lightly doped N-type drain region; forming an insulation spacer surrounding the gate region; performing large tilt heavily-doped P ion implantation in an inclined direction via a mask with an opening at the position of the N type Si source region and implanting P ions into the space between the N type Si source region and the N type drain region to form a heavily-doped P-type region; finally forming a metal layer on the N type Si source region, then allowing the reaction between the metal layer and the remained Si material underneath to form silicide by heat treatment. In the device prepared by the method of the present invention, an ohmic contact is formed between the silicide and the heavily-doped P-type region nearby in order to release the holes accumulated in body region of the SOI MOS device and eliminate floating body effects thereof. Besides, the device of the present invention also has following advantages, such as limited chip area, simplified fabricating process and great compatibility with traditional CMOS technology.

摘要翻译： 本发明公开了一种具有源/体欧姆接触的SOI MOS器件的制造方法。 该制造方法包括以下步骤：首先产生栅极区域，然后进行高剂量源和漏极掺杂以形成轻掺杂的N型源极区域和轻掺杂的N型漏极区域; 形成围绕所述栅极区域的绝缘间隔物; 通过在N型Si源极区域的位置处具有开口的掩模在倾斜方向上进行大倾斜重掺杂P离子注入，并且将P离子注入到N型Si源极区域和N型漏极区域之间的空间中，以 形成重掺杂P型区; 最后在N型Si源区上形成金属层，然后通过热处理使金属层与下面残留的Si材料之间的反应形成硅化物。 在通过本发明的方法制备的器件中，在硅化物和附近的重掺杂P型区域之间形成欧姆接触，以释放积累在SOI MOS器件的体区中的空穴并消除浮体效应 其中。 此外，本发明的器件还具有以下优点，例如有限的芯片面积，简化的制造工艺和与传统CMOS技术的很好的兼容性。

公开(公告)号：US08076699B2

公开(公告)日：2011-12-13

申请号：US12414865

申请日：2009-03-31

申请人： Jing Chen ,  Wanjun Chen ,  Chunhua Zhou

发明人： Jing Chen ,  Wanjun Chen ,  Chunhua Zhou

IPC分类号： H01L29/778 ,  H01L21/335

CPC分类号： H01L27/0605 ,  H01L27/0629 ,  H01L29/2003 ,  H01L29/7787 ,  H01L29/872

摘要： Integrated high efficiency lateral field effect rectifier and HEMT devices of GaN or analogous semiconductor material, methods for manufacturing thereof, and systems which include such integrated devices. The lateral field effect rectifier has an anode containing a shorted ohmic contact and a Schottky contact, and a cathode containing an ohmic contact, while the HEMT preferably has a gate containing a Schottky contact. Two fluorine ion containing regions are formed directly underneath both Schottky contacts in the rectifier and in the HEMT, pinching off the (electron gas) channels in both structures at the hetero-interface between the epitaxial layers.

摘要翻译： 集成的高效横向场效应整流器和GaN或类似半导体材料的HEMT器件，其制造方法以及包括这种集成器件的系统。 横向场效应整流器具有包含短路欧姆接触和肖特基接触的阳极和包含欧姆接触的阴极，而HEMT优选地具有包含肖特基接触的栅极。 两个含氟离子的区域直接形成在整流器和HEMT中的两个肖特基触点的正下方，夹在外延层之间的异质界面处的两个结构中的（电子气体）沟道。

公开(公告)号：US20110292723A1

公开(公告)日：2011-12-01

申请号：US12937257

申请日：2010-07-14

申请人： Deyuan Xiao ,  Xiaolu Huang ,  Jing Chen ,  Xi Wang

发明人： Deyuan Xiao ,  Xiaolu Huang ,  Jing Chen ,  Xi Wang

IPC分类号： G11C11/38 ,  H01L21/336 ,  H01L29/772

CPC分类号： H01L29/7841 ,  G11C11/404 ,  G11C2211/4016 ,  H01L27/10802

摘要： The present invention discloses a DRAM cell utilizing floating body effect and a manufacturing method thereof. The DRAM cell includes a P type semiconductor region provided on a buried oxide layer, an N type semiconductor region provided on the P type semiconductor region, a gate region provided on the N type semiconductor region, and an electrical isolation region surrounding the P type semiconductor region and the N type semiconductor region. A diode of floating body effect is taken as a storage node. Via a tunneling effect between bands, electrons gather in the floating body, which is defined as a first storage state; via forward bias of PN junction, electrons are emitted out from the floating body or holes are injected into the floating body, which is defined as a second storage state. The present invention provides a highly efficient DRAM cell utilizing floating body effect with high density, which has low power consumption, has simple manufacturing process, and is compatible to the conventional CMOS and conventional logic circuit manufacturing process.

摘要翻译： 本发明公开了一种利用浮体效应的DRAM单元及其制造方法。 DRAM单元包括设置在掩埋氧化物层上的P型半导体区域，设置在P型半导体区域上的N型半导体区域，设置在N型半导体区域上的栅极区域和围绕P型半导体的电隔离区域 区域和N型半导体区域。 将浮体效应的二极管作为存储节点。 通过带之间的隧道效应，电子聚集在浮体中，其被定义为第一存储状态; 通过PN结的正向偏压，电子从浮体发出，或者将空穴注入到浮动体中，其被定义为第二存储状态。 本发明提供一种利用高密度的浮体效应的高效率DRAM单元，其具有低功耗，制造工艺简单，并且与常规CMOS和常规逻辑电路制造工艺兼容。

公开(公告)号：US20110254101A1

公开(公告)日：2011-10-20

申请号：US12810694

申请日：2010-02-11

申请人： Deyuan Xiao ,  Xi Wang ,  Miao Zhang ,  Jing Chen ,  Zhongying Xue

发明人： Deyuan Xiao ,  Xi Wang ,  Miao Zhang ,  Jing Chen ,  Zhongying Xue

IPC分类号： H01L27/092

CPC分类号： H01L27/1211 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/42392

摘要： A Ge and Si hybrid material inversion mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a circular-shaped cross section and are formed of n-type Ge and p-type Si, respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. In an inversion mode, current flows through the overall cylindrical channel, so as to achieve high carrier mobility, reduce low-frequency noises, prevent polysilicon gate depletion and short channel effects and increase the threshold voltage of the device.

摘要翻译： Ge和Si混合材料反转模式GAA（Gate-All-Around）CMOSFET包括具有第一沟道的PMOS区域，具有第二沟道的NMOS区域和栅极区域。 第一通道和第二通道具有圆形截面并分别由n型Ge和p型Si形成; 第一通道和第二通道的表面基本上被栅极区域包围; 在PMOS区域和NMOS区域之间以及在PMOS或NMOS区域和Si衬底之间设置掩埋氧化物层以将它们彼此隔离。 在反相模式下，电流流过整个圆柱形通道，以实现高载流子迁移率，降低低频噪声，防止多晶硅栅极耗尽和短沟道效应，并增加器件的阈值电压。

公开(公告)号：US20110165870A1

公开(公告)日：2011-07-07

申请号：US13073420

申请日：2011-03-28

申请人： Min Huang ,  Jing Chen ,  Aiqin Zhang ,  Xiaohan Liu

发明人： Min Huang ,  Jing Chen ,  Aiqin Zhang ,  Xiaohan Liu

IPC分类号： H04W76/00

CPC分类号： H04W36/08 ,  H04W12/04 ,  H04W36/0038 ,  H04W36/0088 ,  H04W76/27

摘要： A method, an apparatus and a system for key derivation are disclosed. The method includes the following steps: a target base station) receives multiple keys derived by a source base station, where the keys correspond to cells under control of the target base station; the target base station selects a key corresponding to the target cell after knowing a target cell that a user equipment (UE) wants to access. An apparatus for key derivation and a communications system are also provided.

公开(公告)号：US20110023094A1

公开(公告)日：2011-01-27

申请号：US12892757

申请日：2010-09-28

申请人： Yanmei Yang ,  Yixian Xu ,  Jing Chen

发明人： Yanmei Yang ,  Yixian Xu ,  Jing Chen

IPC分类号： G06F21/00

CPC分类号： H04W12/04 ,  H04W12/10 ,  H04W12/12

摘要： A method for preventing abuse of an Authentication Vector (AV) and a system and apparatus for implementing the method are provided. Access network information of a non-3rd Generation Partnership Project (3GPP) access network where a user resides is bound to an AV of the user, so that when the user accesses an Evolved Packet System (EPS) through the non-3GPP access network, even if an entity in the non-3GPP access network is breached, or an Evolved Packet Data Gateway (ePDG) connected to an untrusted non-3GPP access network is breached, the stolen AV cannot be applied to other non-3GPP access networks by an attacker.

摘要翻译： 提供了防止认证向量（AV）的滥用的方法以及用于实现该方法的系统和装置。 用户驻留的非第三代合作伙伴计划（3GPP）接入网络的接入网络信息被绑定到用户的AV，使得当用户通过非3GPP接入网络访问演进分组系统（EPS）时， 即使违反非3GPP接入网络中的实体，或者违反连接到非信任非3GPP接入网络的演进分组数据网关（ePDG），则被盗AV不能通过以下方式应用于其他非3GPP接入网络 攻击者

公开(公告)号：US07632881B2

公开(公告)日：2009-12-15

申请号：US11425802

申请日：2006-06-22

申请人： Jing Chen ,  Hua Jiao ,  Yegang Lin ,  Jingwu Yang ,  XinMin Yang

发明人： Jing Chen ,  Hua Jiao ,  Yegang Lin ,  Jingwu Yang ,  XinMin Yang

IPC分类号： C08K5/42 ,  C08K5/41 ,  C08G18/42

CPC分类号： C08L53/00 ,  C08K5/42 ,  C08K2201/014 ,  C08L51/04 ,  C08L55/02 ,  C08L69/00 ,  C08L83/04 ,  C08L83/10 ,  C08L2666/14 ,  C08L2666/02 ,  C08L2666/24 ,  C08L83/00

摘要： A polycarbonate composition is disclosed having zero or minimum halogen content, while also exhibiting improved fire-retardance and/or drip-resistant characteristics. The composition comprises an effective amount of a polycarbonate, an anti-dripping agent, an aromatic sulfone sulfonate, an aromatic sulfonate, a synergistic combination of an elastomer-modified graft copolymer and a polysiloxane-polycarbonate copolymer, and an optional siloxane oligomer. The polycarbonate composition is useful for manufacture of electronic and mechanical articles, among others.

摘要翻译： 公开了具有零或最小卤素含量的聚碳酸酯组合物，同时还表现出改善的阻燃性和/或耐滴滴性。 组合物包含有效量的聚碳酸酯，抗滴落剂，芳族磺酸磺酸酯，芳族磺酸酯，弹性体改性的接枝共聚物和聚硅氧烷 - 聚碳酸酯共聚物的协同组合以及任选的硅氧烷低聚物。 聚碳酸酯组合物可用于制造电子和机械制品等。

公开(公告)号：US07553895B2

公开(公告)日：2009-06-30

申请号：US11427472

申请日：2006-06-29

申请人： Yuxian An ,  Jing Chen ,  Hua Jiao ,  Yegang Lin ,  Mahari Tjahjadi ,  XinMin Yang

发明人： Yuxian An ,  Jing Chen ,  Hua Jiao ,  Yegang Lin ,  Mahari Tjahjadi ,  XinMin Yang

IPC分类号： C08L51/00 ,  C08K5/42

CPC分类号： C08L69/00 ,  C08K5/42 ,  C08L27/18 ,  C08L51/04 ,  C08L83/10 ,  C08L2666/02

摘要： A thermoplastic polycarbonate composition is disclosed, in various embodiments, having enhanced low-temperature ductility, UV resistance and/or fire-retardance characteristics. The composition comprises a polycarbonate, and a combination of an elastomer-modified graft copolymer and a polysiloxane-polycarbonate copolymer. The polycarbonate composition is useful for manufacture of electronic and mechanical parts, among others.

摘要翻译： 在各种实施方案中，公开了具有增强的低温延展性，抗紫外线性和/或阻燃特性的热塑性聚碳酸酯组合物。 组合物包含聚碳酸酯，和弹性体改性的接枝共聚物与聚硅氧烷 - 聚碳酸酯共聚物的组合。 聚碳酸酯组合物可用于制造电子和机械部件等。

公开(公告)号：US20090156866A1

公开(公告)日：2009-06-18

申请号：US12232982

申请日：2008-09-26

申请人： Fang Cui ,  Jing Chen ,  Chungu Xia ,  Haixiao Kang ,  Xinzhi Zhang ,  Jin Tong ,  Xuemei Li

发明人： Fang Cui ,  Jing Chen ,  Chungu Xia ,  Haixiao Kang ,  Xinzhi Zhang ,  Jin Tong ,  Xuemei Li

IPC分类号： C07C31/18

CPC分类号： B01J37/18 ,  B01J23/83 ,  B01J37/03 ,  C07C29/60 ,  C07C31/205

摘要： This invention disclosed a method for producing 1,2-propylene glycol from bio-based glycerol. In this method, a CuO—CeO2—SiO2 catalyst is filled into a fixed bed reactor, a glycerol solution is flowed into the reactor together with hydrogen gas in a manner of top feeding, and controlling the reaction temperature to be 170˜200° C., the reaction pressure to be 1.0˜5.0 MPa, so as to realize the production of 1,2-propylene glycol from the hydrogenation of glycerol. The catalyst used in this invention can sustain a high selectivity for the target product and a high conversion for glycerol for 500 hours.

公开(公告)号：US20090113371A1

公开(公告)日：2009-04-30

申请号：US12347832

申请日：2008-12-31

申请人： Limin He ,  So-Zen Yao ,  Wenyong Deng ,  Jing Chen ,  Liang-Jih Chao

发明人： Limin He ,  So-Zen Yao ,  Wenyong Deng ,  Jing Chen ,  Liang-Jih Chao

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： Routing methods for an integrated circuit design layout are disclosed. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the time.

摘要翻译： 公开了集成电路设计布局的布线方法。 布局可以包括设计网表和库单元格。 多级全局路由可以为每个网络生成拓扑线。 可以执行设计上面向图形的基于图形的详细路由。 可以执行详细路由后的路由优化，以进一步提高路由质量。 一些方法可以是单线程的全部或部分时间，和/或多线程的一些或所有的时间。