公开(公告)号：US10748603B2

公开(公告)日：2020-08-18

申请号：US16146473

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Huseyin Ekin Sumbul ,  Gregory K. Chen ,  Raghavan Kumar ,  Phil Knag ,  Abhishek Sharma ,  Sasikanth Manipatruni ,  Amrita Mathuriya ,  Ram Krishnamurthy ,  Ian A. Young

IPC: G11C8/00 ,  G11C11/418 ,  G06F9/30 ,  G11C11/419 ,  G11C13/00 ,  G11C7/10 ,  G11C11/54 ,  G06N3/063 ,  G06N3/08 ,  G11C7/18 ,  G06F7/544 ,  G11C11/16

Abstract: A memory circuit has compute-in-memory circuitry that enables a multiply-accumulate (MAC) operation based on shared charge. Row access circuitry drives multiple rows of a memory array to multiply a first data word with a second data word stored in the memory array. The row access circuitry drives the multiple rows based on the bit pattern of the first data word. Column access circuitry drives a column of the memory array when the rows are driven. Accessed rows discharge the column line in an accumulative fashion. Sensing circuitry can sense voltage on the column line. A processor in the memory circuit computes a MAC value based on the voltage sensed on the column.

公开(公告)号：US10713558B2

公开(公告)日：2020-07-14

申请号：US15395231

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Huseyin Ekin Sumbul ,  Gregory K. Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram K. Krishnamurthy

IPC: G06N3/04 ,  G06N3/063 ,  G06N3/08

Abstract: In one embodiment, a method comprises determining that a membrane potential of a first neuron of a first neuron core exceeds a threshold; determining a first plurality of synapse cores that each store at least one synapse weight associated with the first neuron; and sending a spike message to the determined first plurality of synapse cores.

公开(公告)号：US10482372B2

公开(公告)日：2019-11-19

申请号：US14757397

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Gregory K. Chen ,  Jae-Sun Seo

IPC: G06N3/04 ,  G06N3/02 ,  G06N3/063 ,  G06F13/42

Abstract: Systems and methods for an interconnection scheme for reconfigurable neuromorphic hardware are disclosed. A neuromorphic processor may include a plurality of corelets, each corelet may include a plurality of synapse arrays and a neuron array. Each synapse array may include a plurality of synapses and a synapse array router coupled to synapse outputs in a synapse array. Each synapse may include a synapse input, synapse output; and a synapse memory. A neuron array may include a plurality of neurons, each neuron may include a neuron input and a neuron output. Each synapse array router may include a first logic to route one or more of the synapse outputs to one or more of the neuron inputs.

公开(公告)号：US20190102669A1

公开(公告)日：2019-04-04

申请号：US15721653

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Gregory K. Chen ,  Kshitij Bhardwaj ,  Raghavan Kumar ,  Huseyin E. Sumbul ,  Phil Knag ,  Ram K. Krishnamurthy ,  Himanshu Kaul

IPC: G06N3/04 ,  G06N3/063

Abstract: In one embodiment, a processor comprises a first neuromorphic core to implement a plurality of neural units of a neural network, the first neuromorphic core comprising a memory to store a current time-step of the first neuromorphic core; and a controller to track current time-steps of neighboring neuromorphic cores that receive spikes from or provide spikes to the first neuromorphic core; and control the current time-step of the first neuromorphic core based on the current time-steps of the neighboring neuromorphic cores.

公开(公告)号：US20180189631A1

公开(公告)日：2018-07-05

申请号：US15395231

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Huseyin Ekin Sumbul ,  Gregory K. Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram K. Krishnamurthy

IPC: G06N3/04 ,  G06N3/08

CPC classification number: G06N3/04 ,  G06N3/049 ,  G06N3/063 ,  G06N3/08

Abstract: In one embodiment, a method comprises determining that a membrane potential of a first neuron of a first neuron core exceeds a threshold; determining a first plurality of synapse cores that each store at least one synapse weight associated with the first neuron; and sending a spike message to the determined first plurality of synapse cores.

公开(公告)号：US09992042B2

公开(公告)日：2018-06-05

申请号：US14574189

申请日：2014-12-17

Applicant: Intel Corporation

Inventor： Mark A. Anders ,  Himanshu Kaul ,  Gregory K. Chen

IPC: H04L12/66 ,  H04L12/64 ,  H04L12/933 ,  H04L12/50 ,  H04L12/24 ,  G06F15/78

CPC classification number: H04L12/64 ,  G06F15/7825 ,  H04L12/50 ,  H04L12/6418 ,  H04L12/66 ,  H04L41/02 ,  H04L49/109 ,  Y02D10/12 ,  Y02D10/13

Abstract: A packet-switched request from a first router of a network-on-chip is received. The packet-switched request is generated by source logic of the network-on-chip. Circuit-switched data associated with the packet switched request is also received. The circuit-switched data is stored by a storage element. The circuit-switched data is sent towards destination logic identified in the packet-switched request.

公开(公告)号：US09979668B2

公开(公告)日：2018-05-22

申请号：US14579303

申请日：2014-12-22

Applicant: Intel Corporation

Inventor： Gregory K. Chen ,  Mark A. Anders ,  Himanshu Kaul ,  Ram K. Krishnamurthy ,  Aaron T. Stillmaker

IPC: H04L12/863 ,  H04L12/911 ,  H04L12/935 ,  G06F15/78

CPC classification number: H04L47/625 ,  G06F15/7825 ,  H04L12/6402 ,  H04L47/72 ,  H04L49/30

Abstract: A first packet-switched reservation request is received. Data associated with the first packet-switched reservation request is communicated through a first circuit-switched channel according to a best effort communication scheme. A second packet-switched reservation request is received. Data associated with the second packet-switched reservation request is communicated through a second circuit-switched channel according to a guaranteed throughput communication scheme.

公开(公告)号：US09923730B2

公开(公告)日：2018-03-20

申请号：US14574294

申请日：2014-12-17

Applicant: Intel Corporation

Inventor： Gregory K. Chen ,  Mark A. Anders ,  Himanshu Kaul

IPC: H04L12/28 ,  H04L12/18 ,  H04L12/761 ,  H04L12/933 ,  H04L12/935

CPC classification number: H04L12/1886 ,  H04L45/16 ,  H04L49/109 ,  H04L49/3009

Abstract: A multicast message that is to originate from a source is received. The multicast message comprises an identifier. A plurality of directions in which the multicast message is to fork at the router are stored. A plurality of messages from the directions in which the multicast message is to fork are received. The received messages are to comprise the identifier. The plurality of messages are aggregated into an aggregate message and sent towards the source.

公开(公告)号：US09652425B2

公开(公告)日：2017-05-16

申请号：US14126910

申请日：2013-06-28

Applicant: Intel Corporation

Inventor： Gregory K. Chen ,  Mark A. Anders ,  Himanshu Kaul ,  Sudhir K. Satpathy ,  Ram K. Krishnamurthy

IPC: G06F13/42 ,  G06F13/40 ,  H04L12/933

CPC classification number: G06F13/4022 ,  G06F13/4282 ,  G06F15/7825 ,  H04L12/46 ,  H04L49/109 ,  H04L67/10 ,  Y02D10/12 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: In an embodiment, a router includes multiple input ports and output ports, where the router is of a source-synchronous hybrid network on chip (NoC) to enable communication between routers of the NoC based on transitions in control flow signals communicated between the routers. Other embodiments are described and claimed.

公开(公告)号：US20160182396A1

公开(公告)日：2016-06-23

申请号：US14574258

申请日：2014-12-17

Applicant: Intel Corporation

Inventor： Himanshu Kaul ,  Gregory K. Chen ,  Mark A. Anders

IPC: H04L12/913 ,  H04L12/935 ,  H04L12/933

CPC classification number: H04L47/724 ,  G06F15/7825 ,  H04L12/50 ,  H04L12/6402 ,  H04L12/66 ,  H04L49/109 ,  H04L49/3018 ,  H04L49/3027

Abstract: An apparatus may comprise a plurality of ports and a plurality of channel reservation banks A channel reservation bank is to be associated with a port of the plurality of ports. The channel reservation bank is to comprise a plurality of channel reservation slots. The port of the plurality of ports is to comprise a plurality of circuit-switched channels through the port. The configuration of each of the plurality of circuit-switched channels to be based on information stored in a channel reservation slot of the channel reservation bank to be associated with the port.

Abstract translation: 装置可以包括多个端口和多个信道预留库。信道预留库将与多个端口的端口相关联。 信道预约库包括多个信道预留时隙。 多个端口的端口包括通过端口的多个电路交换信道。 多个电路交换信道中的每一个的配置将基于存储在与端口相关联的信道预留库的信道预留时隙中的信息。