公开(公告)号：US20180122478A1

公开(公告)日：2018-05-03

申请号：US15567942

申请日：2015-05-28

Applicant: Intel Corporation

Inventor： Daniel H. MORRIS ,  Uygar E. AVCI ,  Ian A. YOUNG

IPC: G11C14/00 ,  G11C11/22 ,  H01L27/11502

CPC classification number: G11C14/0072 ,  G11C11/221 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/2275 ,  G11C14/0027 ,  H01L27/11502

Abstract: Described is an apparatus which comprises: a first access transistor controllable by a write word-line (WWL); a second access transistor controllable by a read word-line (RWL); and a ferroelectric cell coupled to the first and second access transistors, wherein the ferroelectric cell is programmable via the WWL and readable via the RWL. Described is a method which comprises: driving a WWL, coupled to a gate terminal of a first access transistor, to cause the first access transistor to turn on; and driving a WBL coupled to a source/drain terminal of the first access transistor, the driven WBL to charge or discharge a storage node coupled to the first access transistor when the first access transistor is turned on, wherein the ferroelectric cell is coupled to the storage node and programmable according to the charged or discharged storage node.

公开(公告)号：US20180086627A1

公开(公告)日：2018-03-29

申请号：US15573342

申请日：2015-06-22

Applicant: Intel Corporation

Inventor： Kevin LAI LIN ,  Chytra PAWASHE ,  Raseong KIM ,  Ian A. YOUNG ,  Kanwal Jit SINGH ,  Robert L. BRISTOL

IPC: B81B7/00 ,  B81C1/00

CPC classification number: B81B7/007 ,  B81B2203/0109 ,  B81B2203/0118 ,  B81B2207/015 ,  B81B2207/07 ,  B81B2207/092 ,  B81B2207/094 ,  B81B2207/095 ,  B81C1/00246 ,  B81C1/00301 ,  B81C2201/0109 ,  B81C2201/014 ,  B81C2203/0714 ,  B81C2203/0742 ,  B81C2203/0771 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76829

Abstract: A conductive layer is deposited into a trench in a sacrificial layer on a substrate. An etch stop layer is deposited over the conductive layer. The sacrificial layer is removed to form a gap. In one embodiment, a beam is over a substrate. An interconnect is on the beam. An etch stop layer is over the beam. A gap is between the beam and the etch stop layer.

公开(公告)号：US20170243917A1

公开(公告)日：2017-08-24

申请号：US15523324

申请日：2014-12-26

Applicant: Intel Corporation

Inventor： Sasikanth MANIPATRUNI ,  Dmitri E. NIKONOV ,  Ian A. YOUNG

IPC: H01L27/22 ,  H03K19/173 ,  H03K19/18

CPC classification number: H01L27/22 ,  H01L27/228 ,  H01L43/08 ,  H03K19/173 ,  H03K19/18

Abstract: An apparatus including a spin to charge conversion node; and a charge to spin conversion node, wherein an input to the spin to charge conversion node produces an output at the charge to spin conversion node. An apparatus including a magnet including an input node and output node, the input node including a capacitor operable to generate magnetic response in the magnet and the output node including at least one spin to charge conversion material. A method including injecting a spin current from a first magnet; converting the spin current into a charge current operable to produce a magnetoelectric interaction with a second magnet; and changing a direction of magnetization of the second magnet in response to the magnetoelectric interaction. A method including injecting a spin current from an input node of a magnet; and converting the spin current into a charge current at an output node of the magnet.