-
公开(公告)号:US20180158588A1
公开(公告)日:2018-06-07
申请号:US15569978
申请日:2015-06-24
Applicant: Intel Corporation
Inventor: Sasikanth MANIPATRUNI , Anurag CHAUDHRY , Dmitri E. NIKONOV , Ian A. YOUNG
CPC classification number: H01F10/3268 , G11C11/155 , G11C11/1675 , H01F10/265 , H01L43/08 , H01L43/10 , H03K19/16 , H03K19/18
Abstract: Described is an apparatus which comprises: an input ferromagnet to receive a first charge current and to produce a corresponding spin current; and a stack of metal layers configured to convert the corresponding spin current to a second charge current, wherein the stack of metal layers is coupled to the input magnet.
-
公开(公告)号:US20170158501A1
公开(公告)日:2017-06-08
申请号:US15301337
申请日:2014-06-27
Applicant: Intel Corporation
Inventor: Jorge A. MUNOZ , Dmitri E. NIKONOV , Kelin J. KUHN , Patrick THEOFANIS , Chytra PAWASHE , Kevin LIN , Seiyon KIM
CPC classification number: B82B1/005 , B81B3/0016 , B81B7/02 , B81B2201/014 , B81B2203/0118 , B82B1/002 , B82B3/0023 , B82Y15/00 , B82Y25/00 , B82Y40/00 , H01H1/0094 , H01H1/54 , H01H59/0009 , H01L29/66227 , H01L29/82 , H01L29/84 , Y10S977/732 , Y10S977/838 , Y10S977/888 , Y10S977/938
Abstract: Nanoelectromechanical (NEMS) devices having nanomagnets for an improved range of operating voltages and improved control of dimensions of a cantilever are described. For example, in an embodiment, a nanoelectromechanical (NEMS) device includes a substrate layer, a first magnetic layer disposed above the substrate layer, a first dielectric layer disposed above the first magnetic layer, a second dielectric disposed above the first dielectric layer, and a cantilever disposed above the second dielectric layer. The cantilever bends from a first position to a second position towards the substrate layer when a voltage is applied to the cantilever.
-
公开(公告)号:US20170148903A1
公开(公告)日:2017-05-25
申请号:US15427968
申请日:2017-02-08
Applicant: Intel Corporation
Inventor: Sasikanth MANIPATRUNI , Dmitri E. NIKONOV , Ian A. YOUNG
CPC classification number: H01L29/66984 , G11C11/16 , G11C11/161 , G11C11/1653 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1697 , H01L27/226 , H01L43/08 , H01L43/10 , H01L43/12 , H03K19/16
Abstract: Described is an apparatus, for spin state element device, which comprises: a variable resistive magnetic (VRM) device to receive a magnetic control signal to adjust resistance of the VRM device; and a magnetic logic gating (MLG) device, coupled to the VRM device, to receive a magnetic logic input and perform logic operation on the magnetic logic input and to drive an output magnetic signal based on the resistance of the VRM device. Described is a magnetic de-multiplexer which comprises: a first VRM device to receive a magnetic control signal to adjust resistance of the first VRM; a second VRM device to receive the magnetic control signal to adjust resistance of the second VRM device; and an MLG device, coupled to the first and second VRM devices, the MLG device having at least two output magnets to output magnetic signals based on the resistances of the first and second VRM devices.
-
公开(公告)号:US20150228323A1
公开(公告)日:2015-08-13
申请号:US14696965
申请日:2015-04-27
Applicant: Intel Corporation
Inventor: Sasikanth MANIPATRUNI , Dmitri E. NIKONOV , Ian A. YOUNG
IPC: G11C11/16
CPC classification number: H01L29/66984 , G11C11/16 , G11C11/161 , G11C11/1653 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1697 , H01L27/226 , H01L43/08 , H01L43/10 , H01L43/12 , H03K19/16
Abstract: Described is an apparatus, for spin state element device, which comprises: a variable resistive magnetic (VRM) device to receive a magnetic control signal to adjust resistance of the VRM device; and a magnetic logic gating (MLG) device, coupled to the VRM device, to receive a magnetic logic input and perform logic operation on the magnetic logic input and to drive an output magnetic signal based on the resistance of the VRM device. Described is a magnetic de-multiplexer which comprises: a first VRM device to receive a magnetic control signal to adjust resistance of the first VRM; a second VRM device to receive the magnetic control signal to adjust resistance of the second VRM device; and an MLG device, coupled to the first and second VRM devices, the MLG device having at least two output magnets to output magnetic signals based on the resistances of the first and second VRM devices.
Abstract translation: 描述了一种用于自旋状态元件器件的装置,其包括:可变电阻磁极(VRM)器件,用于接收磁控制信号以调节VRM器件的电阻; 以及耦合到VRM装置的磁逻辑门控(MLG)装置,以接收磁逻辑输入并对磁逻辑输入执行逻辑运算,并且基于VRM装置的电阻来驱动输出磁信号。 描述的磁解除多路复用器包括:第一VRM装置,用于接收磁控制信号以调整第一VRM的电阻; 第二VRM装置,用于接收所述磁控信号以调整所述第二VRM装置的电阻; 以及耦合到第一和第二VRM装置的MLG装置,MLG装置具有至少两个输出磁体,以基于第一和第二VRM装置的电阻输出磁信号。
-
公开(公告)号:US20190259935A1
公开(公告)日:2019-08-22
申请号:US16346872
申请日:2016-12-23
Applicant: Intel Corporation
Inventor: Jasmeet S. CHAWLA , Sasikanth MANIPATRUNI , Robert L. BRISTOL , Chia-Ching LIN , Dmitri E. NIKONOV , Ian A. YOUNG
Abstract: Magneto-electric spin orbital (MESO) structures having functional oxide vias, and method of fabricating magneto-electric spin orbital (MESO) structures having functional oxide vias, are described. In an example, a magneto-electric spin orbital (MESO) device includes a source region and a drain region in or above a substrate. A first via contact is on the source region. A second via contact is on the drain region, the second via contact laterally adjacent to the first via contact. A plurality of alternating ferromagnetic material lines and non-ferromagnetic conductive lines is above the first and second via contacts. A first of the ferromagnetic material lines is on the first via contact, and a second of the ferromagnetic material lines is on the second via contact. A spin orbit coupling (SOC) via is on the first of the ferromagnetic material lines. A functional oxide via is on the second of the ferromagnetic material lines.
-
公开(公告)号:US20170243917A1
公开(公告)日:2017-08-24
申请号:US15523324
申请日:2014-12-26
Applicant: Intel Corporation
Inventor: Sasikanth MANIPATRUNI , Dmitri E. NIKONOV , Ian A. YOUNG
IPC: H01L27/22 , H03K19/173 , H03K19/18
CPC classification number: H01L27/22 , H01L27/228 , H01L43/08 , H03K19/173 , H03K19/18
Abstract: An apparatus including a spin to charge conversion node; and a charge to spin conversion node, wherein an input to the spin to charge conversion node produces an output at the charge to spin conversion node. An apparatus including a magnet including an input node and output node, the input node including a capacitor operable to generate magnetic response in the magnet and the output node including at least one spin to charge conversion material. A method including injecting a spin current from a first magnet; converting the spin current into a charge current operable to produce a magnetoelectric interaction with a second magnet; and changing a direction of magnetization of the second magnet in response to the magnetoelectric interaction. A method including injecting a spin current from an input node of a magnet; and converting the spin current into a charge current at an output node of the magnet.
-
公开(公告)号:US20170069831A1
公开(公告)日:2017-03-09
申请号:US15119380
申请日:2014-03-25
Applicant: Intel Corporation
Inventor: Dmitri E. NIKONOV , Sasikanth MANIPATRUNI , Ian A. Young
Abstract: Described is an apparatus which comprises: first, second, and third free magnetic layers; a first metal layer of first material coupled to the first and third free magnetic layers; and a second metal layer of second material different from the first material, the second metal layer coupled to the second and third free magnetic layers. Described is an STT majority gate device which comprises: a free magnetic layer in a ring; and first, second, third, and fourth free magnetic layers coupled to the free magnetic layer.
Abstract translation: 描述了一种装置,其包括:第一,第二和第三自由磁性层; 耦合到所述第一和第三自由磁性层的第一材料的第一金属层; 以及与第一材料不同的第二材料的第二金属层,第二金属层耦合到第二和第三自由磁性层。 描述的是STT多数门装置,其包括:环中的自由磁性层; 以及耦合到自由磁性层的第一,第二,第三和第四自由磁性层。
-
公开(公告)号:US20190013063A1
公开(公告)日:2019-01-10
申请号:US16079400
申请日:2016-03-23
Applicant: Intel Corporation
Inventor: Huichu LIU , Sasikanth MANIPATRUNI , Daniel H. MORRIS , Kaushik VAIDYANATHAN , Niloy MUKHERJEE , Dmitri E. NIKONOV , Ian YOUNG , Tanay KARNIK
IPC: G11C11/413 , G11C11/412 , G11C13/00 , G11C14/00 , G11C7/10
CPC classification number: G11C11/413 , G11C7/1045 , G11C7/1057 , G11C7/20 , G11C11/412 , G11C13/0007 , G11C14/009 , G11C2213/70 , G11C2213/71
Abstract: One embodiment provides an apparatus. The apparatus includes a pair of nonvolatile resistive random access memory (RRAM) memory cells coupled to a volatile static RAM (SRAM) memory cell. The pair of nonvolatile RRAM memory cells includes a first RRAM memory cell and a second RRAM memory cell. The first RRAM memory cell includes a first resistive memory element coupled to a first bit line, and a first selector transistor coupled between the first resistive memory element and a first output node of the volatile SRAM memory cell. The second RRAM memory cell includes a second resistive memory element coupled to a second bit line, and a second selector transistor coupled between the second resistive memory element and a second output node of the volatile SRAM memory cell.
-
9.
公开(公告)号:US20180158587A1
公开(公告)日:2018-06-07
申请号:US15569975
申请日:2015-06-24
Applicant: Intel Corporation
Inventor: Sasikanth MANIPATRUNI , Anurag CHAUDHRY , Dmitri E. NIKONOV , David J. MICHALAK , Ian A. YOUNG
CPC classification number: H01F10/3254 , B82Y25/00 , H01F10/1936 , H01F10/30 , H01F10/329 , H01F41/308 , H01L43/08 , H01L43/10 , H01L43/12 , H03K19/16
Abstract: Described is an apparatus which comprises: an input magnet formed of one or more materials with a sufficiently high anisotropy and sufficiently low magnetic saturation to increase injection of spin currents; and a first interface layer coupled to the input magnet, wherein the first interface layer is formed of non-magnetic material such that the first interface layer and the input magnet together have sufficiently matched atomistic crystalline layers.
-
-
-
-
-
-
-
-