公开(公告)号：US20180040719A1

公开(公告)日：2018-02-08

申请号：US15230871

申请日：2016-08-08

Applicant: International Business Machines Corporation

Inventor： Miaomiao Wang ,  Tenko Yamashita ,  Chun-chen Yeh ,  Hui Zang

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/423 ,  H01L21/768

CPC classification number: H01L29/66795 ,  H01L21/743 ,  H01L21/76877 ,  H01L21/76898 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/4232 ,  H01L29/66545

Abstract: In a fin-Field Effect Transistor (finFET), a recess is created at a location of a fin, the fin being coupled to a gate of the finFET, the recess extending into a substrate interfacing with the gate. The recess is filled at least partially with a first conductive material. The first conductive material is insulated from the gate. The fin is replaced with a replacement structure. The replacement structure is electrically connected to the first conductive material using a second conductive material. the second conductive material is insulated from a first surface of the finFET. A first electrical contact structure is fabricated on the first surface. A second electrical contact structure is fabricated on a second surface of the finFET, the second surface being on a different spatial plane than the first surface.

公开(公告)号：US08816428B1

公开(公告)日：2014-08-26

申请号：US13905850

申请日：2013-05-30

Applicant: International Business Machines Corporation ,  Global Foundries Inc.

Inventor： Robert J. Miller ,  Tenko Yamashita ,  Hui Zang

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/762

CPC classification number: H01L29/785 ,  H01L21/30604 ,  H01L21/762 ,  H01L29/66795

Abstract: Methods and systems for forming multigate devices and systems are disclosed. In accordance with one such method, a fin is formed on a semiconductor substrate including a carbon-doped semiconductor layer. Further, a first portion of semiconductor material that is beneath the fin is removed to form a void beneath the fin by etching the material such that the fin is supported by at least one supporting pillar of the semiconducting material and such that the carbon-doped semiconductor layer prevents the etching from removing at least a portion of the fin. A dielectric material is deposited in the void to isolate the fin from a second portion of semiconductor material that is below the void. In addition, source and drain regions are formed in the fin and a gate structure is formed over the fin to fabricate the multigate device such that the dielectric material reduces current leakage beneath the device.

Abstract translation: 公开了用于形成多设备和系统的方法和系统。 根据一种这样的方法，在包括碳掺杂半导体层的半导体衬底上形成翅片。 此外，在翅片下面的半导体材料的第一部分被去除以通过蚀刻材料形成鳍下方的空隙，使得翅片由半导体材料的至少一个支撑柱支撑，并且使得掺杂碳的半导体 层防止蚀刻去除鳍的至少一部分。 在空隙中沉积介电材料以将散热片与空隙下方的半导体材料的第二部分隔离。 此外，源极和漏极区域形成在翅片中，并且在鳍上形成栅极结构以制造多栅极器件，使得介电材料减少器件下方的电流泄漏。

公开(公告)号：US10937786B2

公开(公告)日：2021-03-02

申请号：US16134173

申请日：2018-09-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Ruilong Xie ,  Laertis Economikos

IPC: H01L21/00 ,  H01L27/088 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to gate cut structures and methods of manufacture. The structure includes: a plurality of gate structures comprising source and drain regions and sidewall spacers comprised of different dielectric materials; and contacts connecting to the source and drain regions and isolated from the gate structures by the different dielectric materials.

公开(公告)号：US10937693B2

公开(公告)日：2021-03-02

申请号：US16150026

申请日：2018-10-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Andreas Knorr ,  Haiting Wang ,  Hui Zang

IPC: H01L21/768 ,  H01L29/66 ,  H01L21/285 ,  H01L21/02

Abstract: At least one method, apparatus and system disclosed herein involves forming local interconnect regions during semiconductor device manufacturing. A plurality of fins are formed on a semiconductor substrate. A gate region is over a portion of the fins. A trench silicide (TS) region is formed adjacent a portion of the gate region. The TS region comprises a first TS metal feature and a second TS metal feature. A bi-layer self-aligned contact (SAC) cap is formed over a first portion of the TS region and electrically coupled to a portion of the gate region. A portion of the bi-layer SAC cap is removed to form a first void. A first local interconnect feature is formed in the first void.

公开(公告)号：US10886178B2

公开(公告)日：2021-01-05

申请号：US16109258

申请日：2018-08-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tek Po Rinus Lee ,  Annie Levesque ,  Qun Gao ,  Hui Zang ,  Rishikesh Krishnan ,  Bharat Krishnan ,  Curtis Durfee

IPC: H01L29/167 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L23/532 ,  H01L21/02 ,  H01L29/40 ,  H01L23/535

Abstract: A device including a triple-layer EPI stack including SiGe, Ge, and Si, respectively, with Ga confined therein, and method of production thereof. Embodiments include an EPI stack including a SiGe layer, a Ge layer, and a Si layer over a plurality of fins, the EPI stack positioned between and over a portion of sidewall spacers, wherein the Si layer is a top layer capping the Ge layer, and wherein the Ge layer is a middle layer capping the SiGe layer underneath; and a Ga layer in a portion of the Ge layer between the SiGe layer and the Si layer.

公开(公告)号：US10833171B1

公开(公告)日：2020-11-10

申请号：US16385436

申请日：2019-04-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yanping Shen ,  Jiehui Shu ,  Hui Zang

IPC: H01L29/76 ,  H01L31/062 ,  H01L31/113 ,  H01L29/66 ,  H01L27/108 ,  H01L27/088 ,  H01L21/8234

Abstract: Disclosed is a transistor that includes a sidewall spacer positioned adjacent a sidewall of a gate structure, wherein the sidewall spacer comprises a notch proximate the lower end and wherein the notch is defined by a substantially vertically oriented side surface and a substantially horizontally oriented upper surface. An epi cavity in the substrate includes a substantially vertically oriented cavity sidewall that is substantially vertically aligned with the substantially vertically oriented side surface of the notch and an epi semiconductor material positioned in the epi cavity and in the notch, wherein the epi semiconductor material contacts and engages the substantially vertically oriented side surface of the notch and the substantially horizontally oriented upper surface of the notch.

公开(公告)号：US10825913B2

公开(公告)日：2020-11-03

申请号：US16144275

申请日：2018-09-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Haiting Wang ,  Ruilong Xie

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L27/02 ,  H01L21/8234

Abstract: A method, apparatus, and manufacturing system are disclosed for a fin field effect transistor having a reduced parasitic capacitance between a gate and a source/drain contact. In one embodiment, we disclose a semiconductor device including first and second fins; an isolation structure between the fins; first and second metal gates; a first dielectric body under the first metal gate and on the substrate between the first fin and the second fin, wherein a top of the first dielectric body is below a top of the first metal gate; and a second dielectric body in the second metal gate and on the substrate between the first fin and the second fin, wherein a top of the second dielectric body is at or above a top of the second metal gate.

公开(公告)号：US10825910B1

公开(公告)日：2020-11-03

申请号：US16386545

申请日：2019-04-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Shesh Mani Pandey

IPC: H01L29/82 ,  H01L29/423 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/321 ,  H01L29/78 ,  H01L29/06 ,  H01L21/768

Abstract: Structures for field effect-transistors and methods of forming field-effect transistors. A gate structure includes a gate electrode and a gate dielectric layer that are arranged between a first sidewall spacer and a second sidewall spacer. The gate structure has a top surface that is recessed relative to the first and second sidewall spacers. A gate cap is arranged over a section of the gate structure and over the first and sidewall spacers. The gate cap has a first section of a first width arranged over the section of the gate structure and a second section of a second width arranged over the section of the gate cap, the first sidewall spacer, and the second sidewall spacer. A dielectric liner is arranged between the gate cap and the gate structure, between the gate cap and the first sidewall spacer, and between the gate cap and the second sidewall spacer.

公开(公告)号：US20200335600A1

公开(公告)日：2020-10-22

申请号：US16385436

申请日：2019-04-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yanping Shen ,  Jiehui Shu ,  Hui Zang

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/108

Abstract: Disclosed is a transistor that includes a sidewall spacer positioned adjacent a sidewall of a gate structure, wherein the sidewall spacer comprises a notch proximate the lower end and wherein the notch is defined by a substantially vertically oriented side surface and a substantially horizontally oriented upper surface. An epi cavity in the substrate includes a substantially vertically oriented cavity sidewall that is substantially vertically aligned with the substantially vertically oriented side surface of the notch and an epi semiconductor material positioned in the epi cavity and in the notch, wherein the epi semiconductor material contacts and engages the substantially vertically oriented side surface of the notch and the substantially horizontally oriented upper surface of the notch.

公开(公告)号：US10811409B2

公开(公告)日：2020-10-20

申请号：US16161620

申请日：2018-10-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiehui Shu ,  Hui Zang ,  Guowei Xu ,  Jian Gao

IPC: H01L27/088 ,  H01L29/66 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78

Abstract: Methods of manufacturing FinFETs including providing a precursor FinFET structure having a substrate with fins thereon, S/D junctions on fin tops, an STI layer on the substrate and between fins, a conformal first dielectric layer on the STI layer and S/D junctions, and a second dielectric layer on the first dielectric layer; forming a conformal third dielectric layer on the second dielectric layer and surfaces of the first dielectric layer located above the second dielectric layer; forming a fourth dielectric layer on the third dielectric layer such that third dielectric layer located between adjacent fins is exposed and such that third dielectric layer located above the adjacent fins is exposed; removing the exposed third dielectric layer and the first dielectric layer located thereunder, thereby exposing the S/D junctions; and forming a metal contact on the exposed S/D junctions and the exposed portion of the third dielectric layer between adjacent fins.