公开(公告)号：US20200335592A1

公开(公告)日：2020-10-22

申请号：US16388479

申请日：2019-04-18

Applicant: Intel Corporation

Inventor： Rahul Ramaswamy ,  Nidhi Nidhi ,  Walid M. Hafez ,  Johann Christian Rode ,  Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dasgupta

IPC: H01L29/417 ,  H01L29/778 ,  H01L29/20 ,  H01L29/205

Abstract: Disclosed herein are IC structures, packages, and devices that include transistors, e.g., III-N transistors, having a source region, a drain region (together referred to as “source/drain” (S/D) regions), and a gate stack. In one aspect, a contact to at least one of the S/D regions of a transistor may have a width that is smaller than a width of the S/D region. In another aspect, a contact to a gate electrode material of the gate stack of a transistor may have a width that is smaller than a width of the gate electrode material. Reducing the width of contacts to S/D regions or gate electrode materials of a transistor may reduce the overlap area between various pairs of these contacts, which may, in turn, allow reducing the off-state capacitance of the transistor. Reducing the off-state capacitance of III-N transistors may advantageously allow increasing their switching frequency.

公开(公告)号：US20200335590A1

公开(公告)日：2020-10-22

申请号：US16390819

申请日：2019-04-22

Applicant: Intel Corporation

Inventor： Nidhi Nidhi ,  Marko Radosavljevic ,  Sansaptak Dasgupta ,  Yang Cao ,  Han Wui Then ,  Johann Christian Rode ,  Rahul Ramaswamy ,  Walid M. Hafez ,  Paul B. Fischer

IPC: H01L29/40 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L29/66

Abstract: Disclosed herein are IC structures, packages, and devices that include III-N transistors implementing various means by which their threshold voltage it tuned. In some embodiments, a III-N transistor may include a doped semiconductor material or a fixed charge material included in a gate stack of the transistor. In other embodiments, a III-N transistor may include a doped semiconductor material or a fixed charge material included between a gate stack and a III-N channel stack of the transistor. Including doped semiconductor or fixed charge materials either in the gate stack or between the gate stack and the III-N channel stack of III-N transistors adds charges, which affects the amount of 2DEG and, therefore, affects the threshold voltages of these transistors.

公开(公告)号：US20200312961A1

公开(公告)日：2020-10-01

申请号：US16367549

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Nidhi Nidhi ,  Paul B. Fischer ,  Rahul Ramaswamy ,  Walid M. Hafez ,  Samuel Jack Beach ,  Xiaojun Weng ,  Johann Christian Rode ,  Marko Radosavljevic ,  Sansaptak Dasgupta

IPC: H01L29/10 ,  H01L29/20 ,  H01L29/786 ,  H01L29/778 ,  H01L29/16 ,  H01L29/08 ,  H01L21/8238 ,  H01L27/07

Abstract: Disclosed herein are IC structures, packages, and devices that include thin-film transistors (TFTs) integrated on the same substrate/die/chip as III-N devices, e.g., III-N transistors. In various aspects, TFTs integrated with III-N transistors have a channel and source/drain materials that include one or more of a crystalline material, a polycrystalline semiconductor material, or a laminate of crystalline and polycrystalline materials. In various aspects, TFTs integrated with III-N transistors are engineered to include one or more of 1) graded dopant concentrations in their source/drain regions, 2) graded dopant concentrations in their channel regions, and 3) thicker and/or composite gate dielectrics in their gate stacks.

公开(公告)号：US20200176582A1

公开(公告)日：2020-06-04

申请号：US16209039

申请日：2018-12-04

Applicant: INTEL CORPORATION

Inventor： Johann C. Rode ,  Samuel J. Beach ,  Nidhi Nidhi ,  Rahul Ramaswamy ,  Han Wui Then ,  Walid Hafez

IPC: H01L29/51 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L29/78 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66

Abstract: An integrated circuit includes a gate structure in contact with a portion of semiconductor material between a source region and a drain region. The gate structure includes gate dielectric and a gate electrode. The gate dielectric includes at least two hybrid stacks of dielectric material. Each hybrid stack includes a layer of low-κ dielectric and a layer of high-κ dielectric on the layer of low-κ dielectric, where the layer of high-κ dielectric has a thickness at least two times the thickness of the layer of low-κ dielectric. In some cases, the layer of low-κ dielectric has a thickness no greater than 1.5 nm. The layer of high-κ dielectric may be a composite layer that includes two or more layers of compositionally-distinct materials. The gate structure can be used with any number of transistor configurations but is particularly useful with respect to group III-V transistors.

公开(公告)号：US09911815B2

公开(公告)日：2018-03-06

申请号：US15126812

申请日：2014-06-18

Applicant: INTEL CORPORATION

Inventor： Nidhi Nidhi ,  Chia-Hong Jan ,  Walid M. Hafez

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L21/265 ,  H01L23/66

CPC classification number: H01L29/402 ,  H01L21/26513 ,  H01L23/66 ,  H01L29/1083 ,  H01L29/401 ,  H01L29/404 ,  H01L29/408 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4983 ,  H01L29/66545 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

Abstract: Planar and non-planar field effect transistors with extended-drain structures, and techniques to fabricate such structures. In an embodiment, a field plate electrode is disposed over an extended-drain, with a field plate dielectric there between. The field plate is disposed farther from the transistor drain than the transistor gate. In a further embodiment, an extended-drain transistor has source and drain contact metal at approximately twice a pitch, of the field plate and the source and/or drain contact metal. In a further embodiment, an isolation dielectric distinct from the gate dielectric is disposed between the extended-drain and the field plate. In a further embodiment, the field plate may be directly coupled to one or more of the transistor gate electrode or a dummy gate electrode without requiring upper level interconnection. In an embodiment, a deep well implant may be disposed between a lightly-doped extended-drain and a substrate to reduce drain-body junction capacitance and improve transistor performance.