公开(公告)号：US08176444B2

公开(公告)日：2012-05-08

申请号：US12426475

申请日：2009-04-20

Applicant: Shayak Banerjee ,  Dureseti Chidambarrao ,  James A. Culp ,  Praveen Elakkumanan ,  Saibal Mukhopadhyay

Inventor： Shayak Banerjee ,  Dureseti Chidambarrao ,  James A. Culp ,  Praveen Elakkumanan ,  Saibal Mukhopadhyay

IPC: G06F17/50

CPC classification number: G06F17/5009 ,  G06F2217/10

Abstract: A method for implementing systematic, variation-aware integrated circuit extraction includes inputting a set of processing conditions to a plurality of variation models, each model corresponding to a separate systematic, parametric variation associated with semiconductor manufacturing of an integrated circuit layout; generating, for each variation model, a netlist update attributable to the associated variation, wherein the netlist update is an update with respect to an original netlist extracted from the integrated circuit layout; and storing the netlist updates generated for each of the processing conditions.

Abstract translation: 一种用于实现系统的变异感知集成电路提取的方法包括：将一组处理条件输入到多个变化模型，每个模型对应于与集成电路布局的半导体制造相关联的单独的系统参数变化; 针对每个变化模型生成归因于相关变化的网表更新，其中网表更新是相对于从集成电路布局提取的原始网表的更新; 以及存储针对每个处理条件生成的网表更新。

公开(公告)号：US20090282380A1

公开(公告)日：2009-11-12

申请号：US12117761

申请日：2008-05-09

Applicant: Laura S. Chadwick ,  James A. Culp ,  David J. Hathaway ,  Anthony D. Polson

Inventor： Laura S. Chadwick ,  James A. Culp ,  David J. Hathaway ,  Anthony D. Polson

IPC: G06F17/50

CPC classification number: G06F17/5068

Abstract: Disclosed is a method of laying out individual cells of an integrated circuit design, based at least in part on the known polysilicon perimeter densities of those cells. That is, the method embodiments use the knowledge of polysilicon perimeter density for known cells to drive placement of those cells on a chip (i.e., to drive floor-planning). The method embodiments can be used to achieve approximately uniform across-chip polysilicon perimeter density and, thereby to limit performance parameter variations between functional devices that are attributable to variations in polysilicon perimeter density. Alternatively, the method embodiments can be used to selectively control variations in the average polysilicon perimeter density of different regions of a chip and, thereby to selectively control certain performance parameter variations between functional devices located in those different regions.

Abstract translation: 公开了至少部分地基于这些单元的已知多晶硅周边密度来布置集成电路设计的单个单元的方法。 也就是说，方法实施例使用已知单元的多晶硅周密度的知识来驱动这些单元在芯片上的放置（即，驱动楼层规划）。 方法实施例可以用于实现大致均匀的跨芯片多晶硅周边密度，并且由此限制可归因于多晶硅周边密度变化的功能器件之间的性能参数变化。 或者，方法实施例可以用于选择性地控制芯片的不同区域的平均多晶硅周长密度的变化，从而选择性地控制位于那些不同区域中的功能设备之间的某些性能参数变化。

公开(公告)号：US20090210834A1

公开(公告)日：2009-08-20

申请号：US12031734

申请日：2008-02-15

Applicant: Laura S. Chadwick ,  James A. Culp ,  Anthony D. Polson

Inventor： Laura S. Chadwick ,  James A. Culp ,  Anthony D. Polson

IPC: G06F9/45

CPC classification number: G06F17/5081

Abstract: IC chip design modeling using perimeter density to an electrical characteristic correlation is disclosed. In one embodiment, a method may include determining a perimeter density of conductive structure within each region of a plurality of regions of an integrated circuit (IC) chip design; correlating a measured electrical characteristic within a respective region of an IC chip that is based on the IC chip design to the perimeter density; and modeling the IC chip design based on the correlation.

Abstract translation: 公开了使用周界密度到电特性相关性的IC芯片设计建模。 在一个实施例中，一种方法可以包括确定集成电路（IC）芯片设计的多个区域的每个区域内的导电结构的周边密度; 将基于IC芯片设计的IC芯片的相应区域中的测量电特性与周围密度相关联; 并根据相关性对IC芯片设计进行建模。

公开(公告)号：US20090193387A1

公开(公告)日：2009-07-30

申请号：US12019125

申请日：2008-01-24

Applicant: Maharaj Mukherjee ,  James A. Culp ,  Alan E. Rosenbluth

Inventor： Maharaj Mukherjee ,  James A. Culp ,  Alan E. Rosenbluth

IPC: G06F17/50

CPC classification number: G03F1/36 ,  G03F1/44 ,  G03F1/68

Abstract: A method is provided for designing a mask that includes the use of a pixel-based simulation of a lithographic process model, in which test structures are designed for determining numerical and discretization errors associated with the pixel grid as opposed to other model inaccuracies. The test structure has a plurality of rows of the same sequence of features, but each row is offset from other rows along an x-direction by a multiple of a minimum step size, such as used in modifying masks during optical proximity correction. The images for each row are simulated with a lithographic model that uses the selected pixel-grid size and the differences between row images are compared. If the differences between rows exceed or violate a predetermined criterion, the pixel grid size may be modified to minimize discretization and/or numerical errors due to the choice of pixel grid size.

Abstract translation: 提供了一种用于设计包括使用光刻处理模型的基于像素的仿真的掩模的方法，其中测试结构被设计用于确定与像素网格相关的数值和离散化误差，而不是其他模型不准确。 测试结构具有相同序列特征的多行，但是每一行都沿x方向与其他行偏移最小步长的倍数，例如在光学邻近校正期间用于修改掩模。 使用所选择的像素网格大小的光刻模型来模拟每行的图像，并比较行图像之间的差异。 如果行之间的差异超过或违反预定标准，则可以修改像素网格大小以使由于像素网格大小的选择而导致的离散化和/或数值误差最小化。

公开(公告)号：US07269808B2

公开(公告)日：2007-09-11

申请号：US10908786

申请日：2005-05-26

Applicant: James A. Bruce ,  James A. Culp ,  John D. Nickel ,  Jacek G. Smolinski

Inventor： James A. Bruce ,  James A. Culp ,  John D. Nickel ,  Jacek G. Smolinski

IPC: G06F17/50

CPC classification number: G06F17/5081

Abstract: A design verification method, including (a) providing in a design a design electrically conducting line and a design contact region being in direct physical contact with the design electrically conducting line; (b) modeling a simulated electrically conducting line of the design electrically conducting line; (c) simulating a possible contact region of the design contact region, wherein the design contact region and the possible contact region are not identical; and (d) determining that the design electrically conducting line and the design contact region are potentially defective if an interfacing surface area of the simulated electrically conducting line and the possible contact region is less than a pre-specified value.

Abstract translation: 一种设计验证方法，包括（a）在设计中提供与设计导电线直接物理接触的设计导电线和设计接触区; （b）对设计导电线的模拟导电线进行建模; （c）模拟设计接触区域的可能的接触区域，其中设计接触区域和可能的接触区域不相同; 以及（d）如果所述模拟导电线路和所述可能接触区域的接口表面积小于预定值，则确定所述设计导电线路和所述设计接触区域具有潜在的缺陷。

公开(公告)号：US06750109B2

公开(公告)日：2004-06-15

申请号：US10064305

申请日：2002-07-01

Applicant: James A. Culp ,  Jawahar P. Nayak ,  Werner A. Rausch ,  Melanie J. Sherony ,  Steven H. Voldman ,  Noah D. Zamdmer

Inventor： James A. Culp ,  Jawahar P. Nayak ,  Werner A. Rausch ,  Melanie J. Sherony ,  Steven H. Voldman ,  Noah D. Zamdmer

IPC: H01L21331

CPC classification number: H01L29/4966 ,  H01L29/1083 ,  H01L29/7835

Abstract: A semiconductor chip includes a semiconductor substrate having a rectifying contact diffusion and a non-rectifying contact diffusion. A halo diffusion is adjacent the rectifying contact diffusion and no halo diffusion is adjacent the non-rectifying contact diffusion. The rectifying contact diffusion can be a source/drain diffusion of an FET to improve resistance to punch-through. The non-rectifying contact diffusion may be an FET body contact, a lateral diode contact, or a resistor or capacitor contact. Avoiding a halo for non-rectifying contacts reduces series resistance and improves device characteristics. In another embodiment on a chip having devices with halos adjacent diffusions, no halo diffusion is adjacent a rectifying contact diffusion of a lateral diode, significantly improving ideality of the diode and increasing breakdown voltage.

Abstract translation: 半导体芯片包括具有整流接触扩散和非整流接触扩散的半导体衬底。 光晕扩散与整流接触扩散相邻，并且没有晕圈扩散与非整流接触扩散相邻。 整流接触扩散可以是FET的源极/漏极扩散，以提高耐穿透性。 非整流接触扩散可以是FET体接触，横向二极管接触或电阻或电容器接触。 避免使用非整流触点的光圈可以降低串联电阻并提高器件特性。 在具有相邻扩散的光晕的器件的芯片的另一实施例中，没有卤素扩散与横向二极管的整流接触扩散相邻，从而显着地提高了二极管的理想性并增加了击穿电压。

公开(公告)号：US06541166B2

公开(公告)日：2003-04-01

申请号：US09766005

申请日：2001-01-18

Applicant: Scott M. Mansfield ,  Timothy A. Brunner ,  James A. Culp ,  Alfred K. Wong

Inventor： Scott M. Mansfield ,  Timothy A. Brunner ,  James A. Culp ,  Alfred K. Wong

IPC: G03F900

CPC classification number: G03F7/70433 ,  G03F1/70 ,  G03F7/70466 ,  H01J37/3026 ,  H01J2237/31761

Abstract: The present invention relates generally to a method for lithographically printing a mask pattern on a substrate, in particular a semiconductor substrate, wherein the mask pattern includes features with diverse pitches. These features may include device features such as vias or contact holes and lines in integrated circuits. The method comprises splitting the mask pattern into a plurality of masks, wherein one or more of the masks contains relatively tightly nested features and one or more of the masks contains relatively isolated features. Each of the plurality of masks is then successively exposed on a photoresist layer on the substrate. For each exposure, the exposure conditions, photoresist layer, other thin films layers, etching process, mask writing process, and/or mask pattern bias may be optimized for the tightly nested feature pattern or isolated feature pattern.

公开(公告)号：US08418087B2

公开(公告)日：2013-04-09

申请号：US13371537

申请日：2012-02-13

Applicant: Shayak Banerjee ,  Dureseti Chidambarrao ,  James A. Culp ,  Praveen Elakkumanan ,  Saibal Mukhopadhyay

Inventor： Shayak Banerjee ,  Dureseti Chidambarrao ,  James A. Culp ,  Praveen Elakkumanan ,  Saibal Mukhopadhyay

IPC: G06F17/50

CPC classification number: G06F17/5009 ,  G06F2217/10

Abstract: A method for implementing systematic, variation-aware integrated circuit extraction includes inputting a set of processing conditions to a plurality of variation models, each model corresponding to a separate systematic, parametric variation associated with semiconductor manufacturing of an integrated circuit layout; generating, for each variation model, a netlist update attributable to the associated variation, wherein the netlist update is an update with respect to an original netlist extracted from the integrated circuit layout; and storing the netlist updates generated for each of the processing conditions.

Abstract translation: 一种用于实现系统的变异感知集成电路提取的方法包括：将一组处理条件输入到多个变化模型，每个模型对应于与集成电路布局的半导体制造相关联的单独的系统参数变化; 针对每个变化模型生成归因于相关变化的网表更新，其中网表更新是相对于从集成电路布局提取的原始网表的更新; 以及存储针对每个处理条件生成的网表更新。

公开(公告)号：US08301290B2

公开(公告)日：2012-10-30

申请号：US12603679

申请日：2009-10-22

Applicant: James A. Culp ,  John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin

Inventor： James A. Culp ,  John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin

IPC: G06F19/00

CPC classification number: G06F17/5068 ,  G06F2217/10

Abstract: Disclosed are a system and a method of correcting systematic, design-based, parametric variations on integrated circuit chips to minimize circuit limited yield loss. Processing information and a map of a chip are stored. The processing information can indicate an impact, on a given device parameter, of changes in a value for a specification associated with a given process step. The map can indicate regional variations in the device parameter (e.g., threshold voltage). Based on the processing information and using the map as a guide, different values for the specification are determined, each to be applied in a different region of the integrated circuit chip during the process step in order to offset the mapped regional parametric variations. A process tool can then be selectively controlled to ensure that during chip manufacturing the process step is performed accordingly and, thereby to ensure that the regional parametric variations are minimized.

Abstract translation: 公开了一种用于校正集成电路芯片上的系统的，基于设计的参数变化的系统和方法，以最小化电路限制的产量损失。 存储处理信息和芯片的映射。 处理信息可以指示给定设备参数对与给定过程步骤相关联的规范的值的变化的影响。 地图可以指示设备参数中的区域变化（例如，阈值电压）。 基于处理信息并使用该图作为指导，确定规范的不同值，每个值在处理步骤期间应用于集成电路芯片的不同区域，以便抵消映射的区域参数变化。 然后可以选择性地控制处理工具，以确保在芯片制造期间相应地执行工艺步骤，从而确保区域参数变化最小化。

公开(公告)号：US08161422B2

公开(公告)日：2012-04-17

申请号：US12349108

申请日：2009-01-06

Applicant: Maharaj Mukherjee ,  James A. Culp ,  Scott M. Mansfield ,  Kafai Lai ,  Alan E. Rosenbluth

Inventor： Maharaj Mukherjee ,  James A. Culp ,  Scott M. Mansfield ,  Kafai Lai ,  Alan E. Rosenbluth

IPC: G06F17/50

CPC classification number: G03F1/36 ,  G03F1/70

Abstract: A method is provided for modeling lithographic processes in the design of photomasks for the manufacture of semiconductor integrated circuits, and more particularly for simulating intermediate range flare effects. For a region of influence (ROI) from first ROI1 of about 5λ/NA to distance ROI2 when the point spread function has a slope that is slowly varying according to a predetermined criterion, then mask shapes at least within the distance range from ROI1 to ROI2 are smoothed prior to computing the SOCS convolutions. The method provides a fast method for simulating intermediate range flare effects with sufficient accuracy.

Abstract translation: 提供了一种用于在用于制造半导体集成电路的光掩模的设计中对光刻工艺进行建模的方法，更具体地说，用于模拟中间范围闪光效应。 对于当点扩散函数具有根据预定标准缓慢变化的斜率时，从约5λ/ NA的第一ROI1到距离ROI2的影响区域（ROI），则至少在从ROI1到ROI2的距离范围内的掩模形状 在计算SOCS卷积之前进行平滑处理。 该方法提供了一种用于以足够的精度模拟中等范围闪光效果的快速方法。