公开(公告)号：US06750109B2

公开(公告)日：2004-06-15

申请号：US10064305

申请日：2002-07-01

申请人： James A. Culp ,  Jawahar P. Nayak ,  Werner A. Rausch ,  Melanie J. Sherony ,  Steven H. Voldman ,  Noah D. Zamdmer

发明人： James A. Culp ,  Jawahar P. Nayak ,  Werner A. Rausch ,  Melanie J. Sherony ,  Steven H. Voldman ,  Noah D. Zamdmer

IPC分类号： H01L21331

CPC分类号： H01L29/4966 ,  H01L29/1083 ,  H01L29/7835

摘要： A semiconductor chip includes a semiconductor substrate having a rectifying contact diffusion and a non-rectifying contact diffusion. A halo diffusion is adjacent the rectifying contact diffusion and no halo diffusion is adjacent the non-rectifying contact diffusion. The rectifying contact diffusion can be a source/drain diffusion of an FET to improve resistance to punch-through. The non-rectifying contact diffusion may be an FET body contact, a lateral diode contact, or a resistor or capacitor contact. Avoiding a halo for non-rectifying contacts reduces series resistance and improves device characteristics. In another embodiment on a chip having devices with halos adjacent diffusions, no halo diffusion is adjacent a rectifying contact diffusion of a lateral diode, significantly improving ideality of the diode and increasing breakdown voltage.

摘要翻译： 半导体芯片包括具有整流接触扩散和非整流接触扩散的半导体衬底。 光晕扩散与整流接触扩散相邻，并且没有晕圈扩散与非整流接触扩散相邻。 整流接触扩散可以是FET的源极/漏极扩散，以提高耐穿透性。 非整流接触扩散可以是FET体接触，横向二极管接触或电阻或电容器接触。 避免使用非整流触点的光圈可以降低串联电阻并提高器件特性。 在具有相邻扩散的光晕的器件的芯片的另一实施例中，没有卤素扩散与横向二极管的整流接触扩散相邻，从而显着地提高了二极管的理想性并增加了击穿电压。

公开(公告)号：US06429482B1

公开(公告)日：2002-08-06

申请号：US09589719

申请日：2000-06-08

申请人： James A. Culp ,  Jawahar P. Nayak ,  Werner A. Rausch ,  Melanie J. Sherony ,  Steven H. Voldman ,  Noah D. Zamdmer

发明人： James A. Culp ,  Jawahar P. Nayak ,  Werner A. Rausch ,  Melanie J. Sherony ,  Steven H. Voldman ,  Noah D. Zamdmer

IPC分类号： H01L2976

CPC分类号： H01L29/4966 ,  H01L29/1083 ,  H01L29/7835

摘要： A semiconductor chip includes a semiconductor substrate having a rectifying contact diffusion and a non-rectifying contact diffusion. A halo diffusion is adjacent the rectifying contact diffusion and no halo diffusion is adjacent the non-rectifying contact diffusion. The rectifying contact diffusion can be a source/drain diffusion of an FET to improve resistance to punch-through. The non-rectifying contact diffusion may be an FET body contact, a lateral diode contact, or a resistor or capacitor contact. Avoiding a halo for non-rectifying contacts reduces series resistance and improves device characteristics. In another embodiment on a chip having devices with halos adjacent diffusions, no halo diffusion is adjacent a rectifying contact diffusion of a lateral diode, significantly improving ideality of the diode and increasing breakdown voltage.

摘要翻译： 半导体芯片包括具有整流接触扩散和非整流接触扩散的半导体衬底。 卤素扩散与整流接触扩散相邻，并且没有卤素扩散与非整流接触扩散相邻。整流接触扩散可以是FET的源极/漏极扩散，以提高耐穿透性。 非整流接触扩散可以是FET体接触，横向二极管接触或电阻或电容器接触。 避免使用非整流触点的光圈可以降低串联电阻并提高器件特性。 在具有相邻扩散的光晕的器件的芯片的另一实施例中，没有卤素扩散与横向二极管的整流接触扩散相邻，从而显着地提高了二极管的理想性并增加了击穿电压。

公开(公告)号：US20100330763A1

公开(公告)日：2010-12-30

申请号：US12493549

申请日：2009-06-29

申请人： Gregory G. Freeman ,  Shreesh Narasimha ,  Ning Su ,  Hasan M. Nayfeh ,  Nivo Rovedo ,  Werner A. Rausch ,  Jian Yu

发明人： Gregory G. Freeman ,  Shreesh Narasimha ,  Ning Su ,  Hasan M. Nayfeh ,  Nivo Rovedo ,  Werner A. Rausch ,  Jian Yu

IPC分类号： H01L21/336

CPC分类号： H01L21/823425 ,  H01L21/26586 ,  H01L21/823412 ,  H01L29/66492 ,  H01L29/66659

摘要： The present invention provides a method of forming asymmetric field-effect-transistors. The method includes forming at least a first and a second gate-mask stack on top of a semiconductor substrate, wherein the first and second gate-mask stacks include at least, respectively, a first and a second gate conductor of a first and a second transistor and have, respectively, a top surface, a first side, and a second side with the second side being opposite to the first side; performing a first halo implantation from the first side of the first and second gate-mask stacks at a first angle while applying the first gate-mask stack in preventing the first halo implantation from reaching a first source/drain region of the second transistor, wherein the first angle is equal to or larger than a predetermined value; and performing a second halo implantation from the second side of the first and second gate-mask stacks at a second angle, thereby creating halo implant in a second source/drain region of the second transistor, wherein the first and second angles are measured against a normal to the substrate.

摘要翻译： 本发明提供了形成非对称场效应晶体管的方法。 该方法包括在半导体衬底的顶部上形成至少第一和第二栅极掩模叠层，其中第一和第二栅极掩模叠层至少分别包括第一和第二栅极掩模叠层的第一和第二栅极导体 分别具有顶表面，第一侧和第二侧，第二侧与第一侧相对; 以第一角度从第一和第二栅极掩模叠层的第一侧进行第一光晕注入，同时施加第一栅极掩模叠层以防止第一光晕注入到达第二晶体管的第一源极/漏极区域，其中 第一角度等于或大于预定值; 以及以第二角度从所述第一和第二栅极掩模叠层的第二侧执行第二光晕注入，从而在所述第二晶体管的第二源极/漏极区域中产生晕轮注入，其中所述第一和第二角度是针对 与基底垂直。

公开(公告)号：US20080233687A1

公开(公告)日：2008-09-25

申请号：US12132698

申请日：2008-06-04

申请人： Huajie Chen ,  Omer H. Dokumaci ,  Oleg G. Gluschenkov ,  Werner A. Rausch

发明人： Huajie Chen ,  Omer H. Dokumaci ,  Oleg G. Gluschenkov ,  Werner A. Rausch

IPC分类号： H01L21/336

CPC分类号： H01L21/26533 ,  H01L21/02238 ,  H01L21/26513 ,  H01L21/31654 ,  H01L21/31675 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/66636

摘要： A method of forming a field effect transistor creates shallower and sharper junctions, while maximizing dopant activation in processes that are consistent with current manufacturing techniques. More specifically, the invention increases the oxygen content of the top surface of a silicon substrate. The top surface of the silicon substrate is preferably cleaned before increasing the oxygen content of the top surface of the silicon substrate. The oxygen content of the top surface of the silicon substrate is higher than other portions of the silicon substrate, but below an amount that would prevent epitaxial growth. This allows the invention to epitaxially grow a silicon layer on the top surface of the silicon substrate. Further, the increased oxygen content substantially limits dopants within the epitaxial silicon layer from moving into the silicon substrate.

摘要翻译： 形成场效应晶体管的方法产生更浅和更尖的结，同时在与当前制造技术一致的工艺中最大化掺杂剂活化。 更具体地，本发明增加了硅衬底的顶表面的氧含量。 优选在增加硅衬底的顶表面的氧含量之前清洁硅衬底的顶表面。 硅衬底的顶表面的氧含量高于硅衬底的其它部分，但低于防止外延生长的量。 这允许本发明在硅​​衬底的顶表面上外延生长硅层。 此外，增加的氧含量基本上限制外延硅层内的掺杂剂移动到硅衬底中。

公开(公告)号：US07176481B2

公开(公告)日：2007-02-13

申请号：US10905598

申请日：2005-01-12

申请人： Huajie Chen ,  Dureseti Chidambarrao ,  Siddhartha Panda ,  Sang-Hyun Oh ,  Henry K. Utomo ,  Werner A. Rausch

发明人： Huajie Chen ,  Dureseti Chidambarrao ,  Siddhartha Panda ,  Sang-Hyun Oh ,  Henry K. Utomo ,  Werner A. Rausch

IPC分类号： H01L29/06

CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/7848

摘要： Disclosed is an integrated circuit structure and a method of making such a structure that has a substrate and P-type and N-type transistors on the substrate. The N-type transistor extension and source/drain regions comprise dopants implanted into the substrate. The P-type transistor extension and source/drain regions partially include a strained epitaxial silicon germanium, wherein the strained silicon germanium comprises of two layers, with a top layer that is closer to the gate stack than the bottom layer. The strained silicon germanium is in-situ doped and creates longitudinal stress on the channel region.

摘要翻译： 公开了一种集成电路结构以及在衬底上具有衬底和P型和N型晶体管的结构的方法。 N型晶体管延伸和源极/漏极区域包括注入到衬底中的掺杂剂。 P型晶体管延伸和源极/漏极区域部分地包括应变外延硅锗，其中应变硅锗包括两层，顶层比底层更靠近栅极堆叠。 应变硅锗被原位掺杂并在沟道区域上产生纵向应力。

公开(公告)号：US06815282B2

公开(公告)日：2004-11-09

申请号：US10460717

申请日：2003-06-12

申请人： William R. Dachtera ,  Rajiv V. Joshi ,  Werner A. Rausch

发明人： William R. Dachtera ,  Rajiv V. Joshi ,  Werner A. Rausch

IPC分类号： H01L2972

CPC分类号： G11C11/412 ,  H01L27/1104 ,  H01L27/1203

摘要： Silicon on insulator (SOI) field effect transistors (FET) with a shared body contact, a SRAM cell and array including the SOI FETs and the method of forming the SOI FETs. The SRAM cell has a hybrid SOI/bulk structure wherein the source/drain diffusions do not penetrate to the underlying insulator layer, resulting in a FET in the surface of an SOI layer with a body or substrate contact formed at a shared contact. FETs are formed on SOI silicon islands located on a BOX layer and isolated by shallow trench isolation (STI). NFET islands in the SRAM cells include a body contact to a P-type diffusion in the NFET island. Each NFET in the SRAM cells include at least one shallow source/drain diffusion that is shallower than the island thickness. A path remains under the shallow diffusions between NFET channels and the body contact. The P-type body contact diffusion is a deep diffusion, the full thickness of the island. Bit line diffusions shared by SRAM cells on adjacent wordlines may be deep diffusions.

公开(公告)号：US08017483B2

公开(公告)日：2011-09-13

申请号：US12493549

申请日：2009-06-29

申请人： Gregory G. Freeman ,  Shreesh Narasimha ,  Ning Su ,  Hasan M. Nayfeh ,  Nivo Rovedo ,  Werner A. Rausch ,  Jian Yu

发明人： Gregory G. Freeman ,  Shreesh Narasimha ,  Ning Su ,  Hasan M. Nayfeh ,  Nivo Rovedo ,  Werner A. Rausch ,  Jian Yu

IPC分类号： H01L21/336

CPC分类号： H01L21/823425 ,  H01L21/26586 ,  H01L21/823412 ,  H01L29/66492 ,  H01L29/66659

摘要： The present invention provides a method of forming asymmetric field-effect-transistors. The method includes forming at least a first and a second gate-mask stack on top of a semiconductor substrate, wherein the first and second gate-mask stacks include at least, respectively, a first and a second gate conductor of a first and a second transistor and have, respectively, a top surface, a first side, and a second side with the second side being opposite to the first side; performing a first halo implantation from the first side of the first and second gate-mask stacks at a first angle while applying the first gate-mask stack in preventing the first halo implantation from reaching a first source/drain region of the second transistor, wherein the first angle is equal to or larger than a predetermined value; and performing a second halo implantation from the second side of the first and second gate-mask stacks at a second angle, thereby creating halo implant in a second source/drain region of the second transistor, wherein the first and second angles are measured against a normal to the substrate.

摘要翻译： 本发明提供了形成非对称场效应晶体管的方法。 该方法包括在半导体衬底的顶部上形成至少第一和第二栅极掩模叠层，其中第一和第二栅极掩模叠层至少分别包括第一和第二栅极掩模叠层的第一和第二栅极导体 分别具有顶表面，第一侧和第二侧，第二侧与第一侧相对; 以第一角度从第一和第二栅极掩模叠层的第一侧进行第一光晕注入，同时施加第一栅极掩模叠层以防止第一光晕注入到达第二晶体管的第一源极/漏极区域，其中 第一角度等于或大于预定值; 以及以第二角度从所述第一和第二栅极掩模叠层的第二侧执行第二光晕注入，从而在所述第二晶体管的第二源极/漏极区域中产生晕轮注入，其中所述第一和第二角度是针对 与基底垂直。

公开(公告)号：US07700425B2

公开(公告)日：2010-04-20

申请号：US11585361

申请日：2006-10-23

申请人： Tina J. Wagner ,  Werner A. Rausch ,  Sadanand V. Deshpande

发明人： Tina J. Wagner ,  Werner A. Rausch ,  Sadanand V. Deshpande

IPC分类号： H01L21/8238

CPC分类号： H01L29/66772 ,  H01L29/78618

摘要： A method is provided for forming an SOI MOSFET device with a silicon layer formed on a dielectric layer with a gate electrode stack, with sidewall spacers on sidewalls of the gate electrode stack and raised source/drain regions formed on the surface of the silicon layer. The gate electrode stack comprises a gate electrode formed of polysilicon over a gate dielectric layer formed on the surface of the silicon layer. A thin amorphous silicon cap layer is formed in the top surface of the gate electrode by implanting dopant into the surface thereof. A notch is etched into the periphery of the cap layer. A plug of dielectric material is formed in the notch. The sidewalls of the gate electrode are covered by the sidewall spacers which cover a portion of the plug for the purpose of eliminating the exposure of the gate polysilicon so that formation of spurious epitaxial growth during the formation of raised source/drain regions is avoided.

摘要翻译： 提供了一种用于形成具有形成在具有栅极电极堆叠的电介质层上的硅层的SOI MOSFET器件的方法，在栅电极堆叠的侧壁上具有侧壁间隔物，并且形成在硅层的表面上的升高的源极/漏极区域。 栅极电极堆叠包括在形成于硅层的表面上的栅极电介质层上的多晶硅形成的栅电极。 通过将掺杂剂注入到其表面中，在栅电极的顶表面中形成薄的非晶硅覆盖层。 凹口蚀刻到盖层的周边。 在凹口中形成介电材料塞。 栅电极的侧壁被覆盖一部分插塞的侧壁间隔物覆盖，以消除栅极多晶硅的暴露，从而避免在形成升高的源极/漏极区域期间形成假外延生长。

公开(公告)号：US20090090974A1

公开(公告)日：2009-04-09

申请号：US11868567

申请日：2007-10-08

申请人： Gregory Costrini ,  David M. Fried ,  Werner A. Rausch ,  Christopher D. Sheraw

发明人： Gregory Costrini ,  David M. Fried ,  Werner A. Rausch ,  Christopher D. Sheraw

IPC分类号： H01L27/092 ,  H01L21/311

CPC分类号： H01L21/823807 ,  H01L21/31111 ,  H01L29/7843

摘要： A dual stress liner structure having a substantially planar interface between liners and a related method are disclosed. In one embodiment, a dual stress liner structure may include a tensile stress liner over an NFET, the NFET including a PFET adjacent thereto; and a compressive stress liner over the PFET, wherein an upper surface of the compressive stress liner is substantially planar with an upper surface of the tensile stress liner at an interface therebetween.

摘要翻译： 公开了一种在衬垫之间具有基本平坦的界面的双重应力衬垫结构和相关方法。 在一个实施例中，双应力衬垫结构可以包括在NFET上的拉伸应力衬垫，NFET包括与其相邻的PFET; 以及PFET上的压应力衬垫，其中所述压应力衬垫的上表面在其间的界面处与所述拉伸应力衬垫的上表面基本上是平面的。

公开(公告)号：US07135724B2

公开(公告)日：2006-11-14

申请号：US10711637

申请日：2004-09-29

申请人： Huajie Chen ,  Dureseti Chidambarrao ,  Sang-Hyun Oh ,  Siddhartha Panda ,  Werner A. Rausch ,  Tsutomu Sato ,  Henry K. Utomo

发明人： Huajie Chen ,  Dureseti Chidambarrao ,  Sang-Hyun Oh ,  Siddhartha Panda ,  Werner A. Rausch ,  Tsutomu Sato ,  Henry K. Utomo

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L29/6659 ,  H01L21/26506 ,  H01L21/28052 ,  H01L21/28079 ,  H01L21/7624 ,  H01L29/1045 ,  H01L29/165 ,  H01L29/4933 ,  H01L29/495 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： A field effect transistor (“FET”) is provided which includes a gate stack overlying a single-crystal semiconductor region of a substrate, a pair of first spacers disposed over sidewalls of said gate stack, and a pair of regions consisting essentially of a single-crystal semiconductor alloy which are disposed on opposite sides of the gate stack. Each of the semiconductor alloy regions is spaced a first distance from the gate stack. The source region and drain region of the FET are at least partly disposed in respective ones of the semiconductor alloy regions, such that the source region and the drain region are each spaced a second distance from the gate stack by a first spacer of the pair of first spacers, the second distance being different from the first distance.

摘要翻译： 提供场效应晶体管（“FET”），其包括覆盖衬底的单晶半导体区域的栅极堆叠，设置在所述栅极堆叠的侧壁上的一对第一间隔区，以及基本上由单个 晶体半导体合金，其设置在栅叠层的相对侧上。 每个半导体合金区域与栅极叠层隔开第一距离。 FET的源极区域和漏极区域至少部分地设置在半导体合金区域的相应半导体合金区域中，使得源极区域和漏极区域之间的距离与栅极叠层间隔开第二距离， 第一间隔物，第二距离与第一距离不同。