公开(公告)号：US20100269079A1

公开(公告)日：2010-10-21

申请号：US12426475

申请日：2009-04-20

申请人： Shayak Banerjee ,  Dureseti Chidambarrao ,  James A. Culp ,  Praveen Elakkumanan ,  Saibal Mukhopadhyay

发明人： Shayak Banerjee ,  Dureseti Chidambarrao ,  James A. Culp ,  Praveen Elakkumanan ,  Saibal Mukhopadhyay

IPC分类号： G06F17/50

CPC分类号： G06F17/5009 ,  G06F2217/10

摘要： A method for implementing systematic, variation-aware integrated circuit extraction includes inputting a set of processing conditions to a plurality of variation models, each model corresponding to a separate systematic, parametric variation associated with semiconductor manufacturing of an integrated circuit layout; generating, for each variation model, a netlist update attributable to the associated variation, wherein the netlist update is an update with respect to an original netlist extracted from the integrated circuit layout; and storing the netlist updates generated for each of the processing conditions.

摘要翻译： 一种用于实现系统的变异感知集成电路提取的方法包括：将一组处理条件输入到多个变化模型，每个模型对应于与集成电路布局的半导体制造相关联的单独的系统参数变化; 针对每个变化模型生成归因于相关变化的网表更新，其中网表更新是相对于从集成电路布局提取的原始网表的更新; 以及存储针对每个处理条件生成的网表更新。

公开(公告)号：US08418087B2

公开(公告)日：2013-04-09

申请号：US13371537

申请日：2012-02-13

申请人： Shayak Banerjee ,  Dureseti Chidambarrao ,  James A. Culp ,  Praveen Elakkumanan ,  Saibal Mukhopadhyay

发明人： Shayak Banerjee ,  Dureseti Chidambarrao ,  James A. Culp ,  Praveen Elakkumanan ,  Saibal Mukhopadhyay

IPC分类号： G06F17/50

CPC分类号： G06F17/5009 ,  G06F2217/10

摘要： A method for implementing systematic, variation-aware integrated circuit extraction includes inputting a set of processing conditions to a plurality of variation models, each model corresponding to a separate systematic, parametric variation associated with semiconductor manufacturing of an integrated circuit layout; generating, for each variation model, a netlist update attributable to the associated variation, wherein the netlist update is an update with respect to an original netlist extracted from the integrated circuit layout; and storing the netlist updates generated for each of the processing conditions.

摘要翻译： 一种用于实现系统的变异感知集成电路提取的方法包括：将一组处理条件输入到多个变化模型，每个模型对应于与集成电路布局的半导体制造相关联的单独的系统参数变化; 针对每个变化模型生成归因于相关变化的网表更新，其中网表更新是相对于从集成电路布局提取的原始网表的更新; 以及存储针对每个处理条件生成的网表更新。

公开(公告)号：US20120144356A1

公开(公告)日：2012-06-07

申请号：US13371537

申请日：2012-02-13

申请人： Shayak Banerjee ,  Dureseti Chidambarrao ,  James A. Culp ,  Praveen Elakkumanan ,  Saibal Mukhopadhyay

发明人： Shayak Banerjee ,  Dureseti Chidambarrao ,  James A. Culp ,  Praveen Elakkumanan ,  Saibal Mukhopadhyay

IPC分类号： G06F9/455

CPC分类号： G06F17/5009 ,  G06F2217/10

摘要： A method for implementing systematic, variation-aware integrated circuit extraction includes inputting a set of processing conditions to a plurality of variation models, each model corresponding to a separate systematic, parametric variation associated with semiconductor manufacturing of an integrated circuit layout; generating, for each variation model, a netlist update attributable to the associated variation, wherein the netlist update is an update with respect to an original netlist extracted from the integrated circuit layout; and storing the netlist updates generated for each of the processing conditions.

摘要翻译： 一种用于实现系统的变异感知集成电路提取的方法包括：将一组处理条件输入到多个变化模型，每个模型对应于与集成电路布局的半导体制造相关联的单独的系统参数变化; 针对每个变化模型生成归因于相关变化的网表更新，其中网表更新是相对于从集成电路布局提取的原始网表的更新; 以及存储针对每个处理条件生成的网表更新。

公开(公告)号：US08176444B2

公开(公告)日：2012-05-08

申请号：US12426475

申请日：2009-04-20

申请人： Shayak Banerjee ,  Dureseti Chidambarrao ,  James A. Culp ,  Praveen Elakkumanan ,  Saibal Mukhopadhyay

发明人： Shayak Banerjee ,  Dureseti Chidambarrao ,  James A. Culp ,  Praveen Elakkumanan ,  Saibal Mukhopadhyay

IPC分类号： G06F17/50

CPC分类号： G06F17/5009 ,  G06F2217/10

摘要： A method for implementing systematic, variation-aware integrated circuit extraction includes inputting a set of processing conditions to a plurality of variation models, each model corresponding to a separate systematic, parametric variation associated with semiconductor manufacturing of an integrated circuit layout; generating, for each variation model, a netlist update attributable to the associated variation, wherein the netlist update is an update with respect to an original netlist extracted from the integrated circuit layout; and storing the netlist updates generated for each of the processing conditions.

摘要翻译： 一种用于实现系统的变异感知集成电路提取的方法包括：将一组处理条件输入到多个变化模型，每个模型对应于与集成电路布局的半导体制造相关联的单独的系统参数变化; 针对每个变化模型生成归因于相关变化的网表更新，其中网表更新是相对于从集成电路布局提取的原始网表的更新; 以及存储针对每个处理条件生成的网表更新。

公开(公告)号：US07673195B2

公开(公告)日：2010-03-02

申请号：US11866502

申请日：2007-10-03

申请人： Ching-Te K. Chuang ,  Jae-Joon Kim ,  Saibal Mukhopadhyay

发明人： Ching-Te K. Chuang ,  Jae-Joon Kim ,  Saibal Mukhopadhyay

IPC分类号： G11C29/00 ,  G11C7/06

CPC分类号： G11C29/50 ,  G11C11/41 ,  G11C29/12005 ,  G11C2029/5002

摘要： A circuit includes a comparator circuit configured such that its output toggles from a first digital logical level to a second digital logical level when its first and second inputs transition between a first state wherein the first input has an applied voltage greater than an applied voltage at the second input and a second state wherein the first input has an applied voltage less than an applied voltage at the second input. A plurality of cells each have at least one series-connected pair of field effect transistors interconnected at an output node intermediate the field effect transistors. Decoding logic is configured to select a given one of the cells for measurement, and selectively interconnect the output node of the given one of the cells to the first input of the comparator circuit. Voltage supply circuitry is configured to (i) apply voltages to the gates of the pair of transistors of the given one of the cells selected for measurement, such that the pair of transistors operate in a linear region, and have a variable voltage difference, Δ, between their gate-to-source voltages, and (ii) vary the Δ until the comparator circuit output toggles from the first digital logical level to the second digital logical level.

摘要翻译： 电路包括比较器电路，其被配置为使得当其第一和第二输入在第一状态和第二输入之间转变时，其输出从第一数字逻辑电平切换到第二数字逻辑电平，其中第一输入具有大于施加电压的施加电压 第二输入和第二状态，其中第一输入具有小于第二输入处的施加电压的施加电压。 多个单元各自具有在场效应晶体管之间的输出节点处互连的至少一个串联连接的场效应晶体管。 解码逻辑被配置为选择用于测量的给定的一个单元，并且将所述单元中的给定单元的输出节点选择性地互连到比较器电路的第一输入。 电压供应电路被配置为（i）向被选择用于测量的给定一个单元的一对晶体管的栅极施加电压，使得该对晶体管在线性区域中工作，并且具有可变电压差＆Dgr ;在它们的栅 - 源电压之间，和（ii）改变＆Dgr; 直到比较器电路输出从第一数字逻辑电平切换到第二数字逻辑电平。

公开(公告)号：US20090310430A1

公开(公告)日：2009-12-17

申请号：US12542187

申请日：2009-08-17

申请人： Ching-Te K. Chuang ,  Jae-Joon Kim ,  Saibal Mukhopadhyay

发明人： Ching-Te K. Chuang ,  Jae-Joon Kim ,  Saibal Mukhopadhyay

IPC分类号： G11C29/00 ,  G01R19/00 ,  G11C11/00 ,  G01R31/08

CPC分类号： G11C29/50 ,  G11C11/41 ,  G11C29/12005 ,  G11C2029/5002

摘要： A circuit includes a comparator circuit configured such that its output toggles from a first digital logical level to a second digital logical level when its first and second inputs transition between a first state wherein the first input has an applied voltage greater than an applied voltage at the second input and a second state wherein the first input has an applied voltage less than an applied voltage at the second input. A plurality of cells each have at least one series-connected pair of field effect transistors interconnected at an output node intermediate the field effect transistors. Decoding logic is configured to select a given one of the cells for measurement, and selectively interconnect the output node of the given one of the cells to the first input of the comparator circuit. Voltage supply circuitry is configured to (i) apply voltages to the gates of the pair of transistors of the given one of the cells selected for measurement, such that the pair of transistors operate in a linear region, and have a variable voltage difference, Δ, between their gate-to-source voltages, and (ii) vary the Δ until the comparator circuit output toggles from the first digital logical level to the second digital logical level.

摘要翻译： 电路包括比较器电路，其被配置为使得当其第一和第二输入在第一状态和第二输入之间转变时，其输出从第一数字逻辑电平切换到第二数字逻辑电平，其中第一输入具有大于施加电压的施加电压 第二输入和第二状态，其中第一输入具有小于第二输入处的施加电压的施加电压。 多个单元各自具有在场效应晶体管之间的输出节点处互连的至少一个串联连接的场效应晶体管。 解码逻辑被配置为选择用于测量的给定的一个单元，并且将所述单元中的给定单元的输出节点选择性地互连到比较器电路的第一输入。 电压供应电路被配置为（i）向被选择用于测量的给定一个单元的一对晶体管的栅极施加电压，使得该对晶体管在线性区域中工作，并且具有可变的电压差 在其栅极至源极电压之间，和（ii）改变增量，直到比较器电路输出从第一数字逻辑电平切换到第二数字逻辑电平。

公开(公告)号：US20070171748A1

公开(公告)日：2007-07-26

申请号：US11337348

申请日：2006-01-23

申请人： Saibal Mukhopadhyay ,  Hamid Mahmoodi ,  Kaushik Roy

发明人： Saibal Mukhopadhyay ,  Hamid Mahmoodi ,  Kaushik Roy

IPC分类号： G11C7/02

CPC分类号： G11C7/065 ,  G11C11/413

摘要： A sense amplifier circuit includes a first double-gate metal oxide semiconductor field effect transistor (DGMOSFET) having a first gate defining a first input to the circuit, a second gate and an output being coupled to a first output of the circuit and a second DGMOSFET having a first gate defining a second input of the circuit, a second gate connected to the output of the first DGMOSFET and an output connected to the second gate of the first DGMOSFET, the output of the second DGMOSFET being coupled to a second output of the circuit.

公开(公告)号：US20090190426A1

公开(公告)日：2009-07-30

申请号：US12019132

申请日：2008-01-24

申请人： Ching-Te K. Chuang ,  Jae-Joon Kim ,  Niladri N. Mojumder ,  Saibal Mukhopadhyay

发明人： Ching-Te K. Chuang ,  Jae-Joon Kim ,  Niladri N. Mojumder ,  Saibal Mukhopadhyay

IPC分类号： G11C29/44

CPC分类号： G11C29/50 ,  G11C11/41 ,  G11C29/028 ,  G11C29/12005 ,  G11C2029/5004 ,  G11C2029/5006

摘要： The circuit includes a static random access memory array having a plurality of cells, in turn having a plurality of devices; as well as a global sensor having at least one output, coupled to the static random access memory array, and configured to sense at least one of global readability and global write-ability. Also included is a decision-making circuit coupled to the at least one output of the global sensor. The decision-making circuit is configured to determine, from the at least one output of the global sensor, whether adaptation signals are required to correct global readability and/or write-ability. An adaptation signal generation block is also included and is coupled to the decision-making circuit and the array, and configured to supply the adaptation signals to the array, responsive to the decision-making circuit determining that the adaptation signals are required. At least the array and the global sensor, and preferably the decision-making circuit and the adaptation signal generation block as well, are implemented on a single integrated circuit chip. An associated method and design structure(s) are also provided.

摘要翻译： 电路包括具有多个单元的静态随机存取存储器阵列，又具有多个器件; 以及具有耦合到静态随机存取存储器阵列并被配置为感测全局可读性和全局写入能力中的至少一个的至少一个输出的全局传感器。 还包括耦合到全球传感器的至少一个输出的决策电路。 决策电路被配置为从全局传感器的至少一个输出确定是否需要自适应信号来校正全局可读性和/或写入能力。 还包括适配信号生成块，并且耦合到决策电路和阵列，并且被配置为响应于决策电路确定需要自适应信号而将适配信号提供给阵列。 至少阵列和全局传感器，以及优选地，决策电路和自适应信号生成块也被实现在单个集成电路芯片上。 还提供了相关联的方法和设计结构。

公开(公告)号：US20090189703A1

公开(公告)日：2009-07-30

申请号：US12021459

申请日：2008-01-29

申请人： Ching-Te K. Chuang ,  Jae-Joon Kim ,  Tae-Hyoung Kim ,  Pong-Fei Lu ,  Saibal Mukhopadhyay ,  Rahul M. Rao ,  Shao-yi Wang

发明人： Ching-Te K. Chuang ,  Jae-Joon Kim ,  Tae-Hyoung Kim ,  Pong-Fei Lu ,  Saibal Mukhopadhyay ,  Rahul M. Rao ,  Shao-yi Wang

IPC分类号： H03K3/03

CPC分类号： H03K3/0315

摘要： A ring oscillator has an odd number of NOR-gates greater than or equal to three, each with first and second input terminals, a voltage supply terminal, and an output terminal. The first input terminals of all the NOR-gates are interconnected, and each of the NOR-gates has its output terminal connected to the second input terminal of an immediately adjacent one of the NOR-gates. During a stress mode, a voltage supply and control block applies a stress enable signal to the interconnected first input terminals, and an increased supply voltage to the voltage supply terminals. During a measurement mode, this block grounds the interconnected first input terminals, and applies a normal supply voltage to the voltage supply terminals. Also included are an analogous NAND-gate based circuit, a circuit combining the NAND- and NOR-aspects, a circuit with a ring oscillator where the inverters may be coupled directly or through inverting paths, and circuits for measuring the bias temperature instability effect in pass gates.

摘要翻译： 环形振荡器具有大于或等于3的奇数NOR门，每个具有第一和第二输入端子，电压源端子和输出端子。 所有NOR门的第一输入端互连，每个NOR门的输出端连接到紧邻的一个NOR门的第二输入端。 在应力模式期间，电压供应和控制块向互连的第一输入端施加应力使能信号，并向电压端提供增加的电源电压。 在测量模式期间，该模块接地互连的第一输入端，并向电源端施加正常的电源电压。 还包括类似的基于NAND栅极的电路，组合NAND和NOR方面的电路，电路与环形振荡器，其中逆变器可以直接耦合或通过反向路径耦合，以及用于测量偏置温度不稳定性效应的电路 通过门。

公开(公告)号：US07319343B2

公开(公告)日：2008-01-15

申请号：US11099386

申请日：2005-04-05

申请人： Swarup Bhunia ,  Hamid Mahmoodi ,  Arijit Raychowhury ,  Saibal Mukhopadhyay ,  Kaushik Roy

发明人： Swarup Bhunia ,  Hamid Mahmoodi ,  Arijit Raychowhury ,  Saibal Mukhopadhyay ,  Kaushik Roy

IPC分类号： H03K19/173 ,  G01R31/28

CPC分类号： G01R31/31858

摘要： A circuit includes an input block and a combinational logic block. The input block has reconfigurable latches that are connected serially during testing times such that an output of one of the latches is connected to an input of a successive latch. The latches are directly connected to first level gates of the combinational logic block. The combinational logic block contains switches that prevent the propagation of signals through the combinational logic block during testing times other than when a desired vector is loaded into the latches. The switches disconnect the power and/or ground from the first level gates. The switches further connect the outputs of the first level gates to power or ground, depending on the type of transistors used in the first level gates. The switches alternatively delay the output through a pair of inverters and resupply the output to itself if refreshing the output is desired.

摘要翻译： 电路包括输入块和组合逻辑块。 输入块具有可重新配置的锁存器，其在测试时间期间串行连接，使得一个锁存器的输出连接到连续锁存器的输入端。 锁存器直接连接到组合逻辑块的第一级门。 组合逻辑块包含开关，其防止在测试期间通过组合逻辑块传播信号，而不是当期望的矢量被加载到锁存器时。 开关从第一级门断开电源和/或接地。 这些开关根据第一级门中使用的晶体管的类型进一步将第一电平门的输出连接到电源或接地。 交换机通过一对逆变器交替地延迟输出，并且如果需要刷新输出，则将输出再供给到其自身。