公开(公告)号：US20090259900A1

公开(公告)日：2009-10-15

申请号：US12405409

申请日：2009-03-17

申请人： Janusz Rajski ,  Jerzy Tyszer ,  Mark Kassab ,  Nilanjan Mukherjee

发明人： Janusz Rajski ,  Jerzy Tyszer ,  Mark Kassab ,  Nilanjan Mukherjee

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G01R31/318335 ,  G01R31/318371 ,  G01R31/318547

摘要： A method for compressing test patterns to be applied to scan chains in a circuit under test. The method includes generating symbolic expressions that are associated with scan cells within the scan chains. The symbolic expressions are created by assigning variables to bits on external input channels supplied to the circuit under test. Using symbolic simulation, the variables are applied to a decompressor to obtain the symbolic expressions. A test cube is created using a deterministic pattern that assigns values to the scan cells to test faults within the integrated circuit. A set of equations is formulated by equating the assigned values in the test cube to the symbolic expressions associated with the corresponding scan cell. The equations are solved to obtain the compressed test pattern.

摘要翻译： 一种用于压缩被测电路中扫描链应用的测试图案的方法。 该方法包括生成与扫描链内的扫描单元相关联的符号表达式。 通过将变量分配给提供给被测电路的外部输入通道上的位来创建符号表达式。 使用符号仿真，将变量应用于解压缩器以获取符号表达式。 使用确定性模式创建测试立方体，该模式为扫描单元分配值以测试集成电路中的故障。 通过将测试立方体中的分配值与与相应扫描单元相关联的符号表达式进行等价来表示一组方程式。 求解等式以获得压缩测试图案。

公开(公告)号：US07506232B2

公开(公告)日：2009-03-17

申请号：US11502655

申请日：2006-08-11

申请人： Janusz Rajski ,  Jerzy Tyszer ,  Mark Kassab ,  Nilanjan Mukherjee

发明人： Janusz Rajski ,  Jerzy Tyszer ,  Mark Kassab ,  Nilanjan Mukherjee

IPC分类号： G01R31/28

CPC分类号： G01R31/318335 ,  G01R31/31813 ,  G01R31/318385 ,  G01R31/318547

摘要： A novel decompressor/PRPG on a microchip performs both pseudo-random test pattern generation and decompression of deterministic test patterns for a circuit-under-test on the chip. The decompressor/PRPG has two phases of operation. In a pseudo-random phase, the decompressor/PRPG generates pseudo-random test patterns that are applied to scan chains within the circuit-under test. In a deterministic phase, compressed deterministic test patterns from an external tester are applied to the decompressor/PRPG. The patterns are decompressed as they are clocked through the decompressor/PRPG into the scan chains. The decompressor/PRPG thus provides much better fault coverage than a simple PRPG, but without the cost of a complete set of fully-specified deterministic test patterns.

摘要翻译： 微芯片上的新型解压缩器/ PRPG对芯片上的电路不足测试的确定性测试模式进行伪随机测试模式生成和解压缩。 解压缩器/ PRPG有两个操作阶段。 在伪随机阶段，解压缩器/ PRPG生成伪随机测试图案，其应用于被测电路中的扫描链。 在确定性阶段，将外部测试仪的压缩确定性测试模式应用于解压缩器/ PRPG。 在通过解压缩器/ PRPG计时到扫描链中时，模式被解压缩。 因此，解压缩器/ PRPG提供比简单PRPG更好的故障覆盖，但是没有完整的完整指定的确定性测试模式的成本。

公开(公告)号：US07500163B2

公开(公告)日：2009-03-03

申请号：US10973522

申请日：2004-10-25

申请人： Janusz Rajski ,  Mark Kassab ,  Nilanjan Mukherjee ,  Jerzy Tyszer

发明人： Janusz Rajski ,  Mark Kassab ,  Nilanjan Mukherjee ,  Jerzy Tyszer

IPC分类号： G01R31/28

CPC分类号： G01R31/318547

摘要： A method and apparatus to compact test responses containing unknown values or multiple fault effects in a deterministic test environment. The proposed selective compactor employs a linear compactor with selection circuitry for selectively passing test responses to the compactor. In one embodiment, gating logic is controlled by a control register, a decoder, and flag registers. This circuitry, in conjunction with any conventional parallel test-response compaction scheme, allows control circuitry to selectively enable serial outputs of desired scan chains to be fed into a parallel compactor at a particular clock rate. A first flag register determines whether all, or only some, scan chain outputs are enabled and fed through the compactor. A second flag register determines if the scan chain selected by the selector register is enabled and all other scan chains are disabled, or the selected scan chain is disabled and all other scan chains are enabled. Other embodiments allow selective masking of a variable number of scan chain outputs.

摘要翻译： 一种在确定性测试环境中压缩包含未知值或多个故障效应的测试响应的方法和装置。 所提出的选择性压实机采用具有用于选择性地将测试响应传递给压实机的选择电路的线性压实机。 在一个实施例中，门控逻辑由控制寄存器，解码器和标志寄存器控制。 该电路结合任何常规的并行测试响应压缩方案，允许控制电路选择性地使所需扫描链的串行输出以特定时钟速率馈送到并联压实机。 第一个标志寄存器确定是否启用所有或只有一些扫描链输出并通过压实器馈送。 第二个标志寄存器确定选择器寄存器选择的扫描链是否启用，所有其他扫描链是禁用的，还是禁用所选扫描链，并启用所有其他扫描链。 其他实施例允许对可变数目的扫描链输出的选择性掩蔽。

公开(公告)号：US20070294327A1

公开(公告)日：2007-12-20

申请号：US11894393

申请日：2007-08-20

申请人： Janusz Rajski ,  Jerzy Tyszer ,  Mark Kassab ,  Nilanjan Mukherjee

发明人： Janusz Rajski ,  Jerzy Tyszer ,  Mark Kassab ,  Nilanjan Mukherjee

IPC分类号： G06F7/58

CPC分类号： G06F7/584 ,  G06F2207/583 ,  H03K3/84

摘要： Method and apparatus for synthesizing high-performance linear finite state machines (LFSMs) such as linear feedback shift registers (LFSRs) or cellular automata (CA). Given a characteristic polynomial for the circuit, the method obtains an original LFSM circuit such as a type I or type II LFSR. Feedback connections within the original circuit are then determined. Subsequently, a number of transformations that shift the feedback connections can be applied in such a way that properties of the original circuit are preserved in a modified LFSM circuit. In particular, if the original circuit is represented by a primitive characteristic polynomial, the method preserves the maximum-length property of the original circuit in the modified circuit and enables the modified circuit to produce the same m-sequence as the original circuit. Through the various transformations, a modified LFSM circuit can be created that provides higher performance through shorter feedback connection lines, fewer levels of logic, and lower internal fan-out.

公开(公告)号：US06557129B1

公开(公告)日：2003-04-29

申请号：US09619988

申请日：2000-07-20

申请人： Janusz Rajski ,  Jerzy Tyszer ,  Mark Kassab ,  Nilanjan Mukherjee

发明人： Janusz Rajski ,  Jerzy Tyszer ,  Mark Kassab ,  Nilanjan Mukherjee

IPC分类号： G01R3128

CPC分类号： G01R31/318547

摘要： A method and apparatus to compact test responses containing unknown values or multiple fault effects in a deterministic test environment. The proposed selective compactor employs a linear compactor with selection circuitry for selectively passing test responses to the compactor. In one embodiment, gating logic is controlled by a control register, a decoder, and flag registers. This circuitry, in conjunction with any conventional parallel test-response compaction scheme, allows control circuitry to selectively enable serial outputs of desired scan chains to be fed into a parallel compactor at a particular clock rate. A first flag register determines whether all, or only some, scan chain outputs are enabled and fed through the compactor. A second flag register determines if the scan chain selected by the selector register is enabled and all other scan chains are disabled, or the selected scan chain is disabled and all other scan chains are enabled. Other embodiments allow selective masking of a variable number of scan chain outputs.

公开(公告)号：US06539409B2

公开(公告)日：2003-03-25

申请号：US09957701

申请日：2001-09-18

申请人： Janusz Rajski ,  Mark Kassab ,  Nilanjan Mukherjee ,  Jerzy Tyszer

发明人： Janusz Rajski ,  Mark Kassab ,  Nilanjan Mukherjee ,  Jerzy Tyszer

IPC分类号： G06F102

CPC分类号： G06F7/584 ,  G06F2207/583 ,  H03K3/84

摘要： Method and apparatus for synthesizing high-performance linear finite state machines (LFSMs) such as linear feedback shift registers (LFSRs) or cellular automata (CA). Given a characteristic polynomial for the circuit, the method obtains an original LFSM circuit such as a type I or type II LFSR. Feedback connections within the original circuit are then determined. Subsequently, a number of transformations that shift the feedback connections can be applied in such a way that properties of the original circuit are preserved in a modified LFSM circuit. In particular, if the original circuit is represented by a primitive characteristic polynomial, the method preserves the maximum-length property of the original circuit in the modified circuit and enables the modified circuit to produce the same m-sequence as the original circuit. Through the various transformations, a modified LFSM circuit can be created that provides higher performance through shorter feedback connection lines, fewer levels of logic, and lower internal fan-out.

公开(公告)号：US09787608B2

公开(公告)日：2017-10-10

申请号：US13276966

申请日：2011-10-19

申请人： Jayakrishna Kidambi ,  Nilanjan Mukherjee ,  Vijoy Pandey

发明人： Jayakrishna Kidambi ,  Nilanjan Mukherjee ,  Vijoy Pandey

IPC分类号： H04L12/28 ,  H04L12/931 ,  H04L12/935

CPC分类号： H04L49/351 ,  H04L49/3054 ,  H04L49/70

摘要： A method and system for configuring communications over a physical communication link connected between a physical port of a network switch and a physical port of a physical network interface on an end station. The communication link between the physical port of the network switch and the physical port of the physical network interface is logically partitioned into a number of channels of communication. For each channel, a channel profile is generated that defines properties of that channel. The physical network interface is instructed to self-configure such that the physical network interface is able to communicate with the network switch over each channel in accordance with the channel profile defined for that channel.

公开(公告)号：US08964600B2

公开(公告)日：2015-02-24

申请号：US13454840

申请日：2012-04-24

申请人： Amitabha Biswas ,  Jayakrishna Kidambi ,  Nilanjan Mukherjee ,  Vijoy A. Pandey

发明人： Amitabha Biswas ,  Jayakrishna Kidambi ,  Nilanjan Mukherjee ,  Vijoy A. Pandey

IPC分类号： H04L12/28 ,  H04L12/715 ,  H04L12/931 ,  H04L12/46 ,  H04L29/08 ,  G06F9/455

CPC分类号： H04L12/4641 ,  G06F9/45558 ,  G06F2009/45595 ,  H04L12/4633 ,  H04L12/4679 ,  H04L45/64 ,  H04L45/74 ,  H04L49/00 ,  H04L49/356 ,  H04L49/70 ,  H04L67/2804

摘要： Methods are provided for overlaying a virtual network on a physical network in a data center environment. An overlay system is arranged in an overlay virtual network to include an overlay agent and an overlay helper. The overlay agent is implemented in an access switch. The overlay helper is implemented in an end station that is in communication with the access switch. Overlay parameters in compliance with an in-band protocol are transmitted between the overlay agent and the overlay helper.

摘要翻译： 提供了用于在数据中心环境中的物理网络上覆盖虚拟网络的方法。 覆盖系统布置在覆盖虚拟网络中以包括覆盖代理和覆盖帮助器。 覆盖代理在接入交换机中实现。 覆盖帮助器在与接入交换机通信的终端站中实现。 覆盖代理和覆盖帮助器之间传输符合带内协议的覆盖参数。

公开(公告)号：US08750307B2

公开(公告)日：2014-06-10

申请号：US13315463

申请日：2011-12-09

申请人： Keshav Kamble ,  Dar-Ren Leu ,  Nilanjan Mukherjee ,  Vijoy A Pandey

发明人： Keshav Kamble ,  Dar-Ren Leu ,  Nilanjan Mukherjee ,  Vijoy A Pandey

IPC分类号： H04L12/28

CPC分类号： H04L41/0654 ,  H04L45/245 ,  H04L45/28 ,  H04L45/66 ,  Y02D50/30

摘要： A switch of a data network implements both a bridge and a virtual bridge. In response to receipt of a data frame by the switch from an external link, the switch performs a lookup in a data structure using a source media access control (SMAC) address specified by the data frame. The switch determines if the external link is configured in a link aggregation group (LAG) and if the SMAC address is newly learned. In response to a determination that the external link is configured in a LAG and the SMAC address is newly learned, the switch associates the SMAC with the virtual bridge and communicates the association to a plurality of bridges in the data network.

摘要翻译： 数据网络的交换机既实现了桥接器又实现了一个虚拟桥接器。 响应于交换机从外部链路接收到数据帧，交换机使用由数据帧指定的源媒体访问控制（SMAC）地址在数据结构中执行查找。 交换机确定在链路聚合组（LAG）中是否配置了外部链路，如果新学习到SMAC地址。 响应于外部链路被配置在LAG中并且新学习到SMAC地址的确定，交换机将SMAC与虚拟网桥相关联，并将该关联传送到数据网络中的多个网桥。

公开(公告)号：US20130242999A1

公开(公告)日：2013-09-19

申请号：US13484216

申请日：2012-05-30

申请人： Keshav G. Kamble ,  Dar-Ren Leu ,  Nilanjan Mukherjee ,  Vijoy A. Pandey

发明人： Keshav G. Kamble ,  Dar-Ren Leu ,  Nilanjan Mukherjee ,  Vijoy A. Pandey

IPC分类号： H04L12/56

CPC分类号： H04L63/101 ,  G06F9/45558 ,  H04L45/64 ,  H04L47/125

摘要： According to one embodiment, a method for providing scalable virtual appliance cloud (SVAC) services includes receiving incoming data traffic having multiple packets directed toward a SVAC using at least one switching distributed line card (DLC), determining that a packet satisfies a condition of an access control list (ACL), designating a destination port to send the packet based on the condition of the ACL being satisfied, fragmenting the packet into cells, wherein the designated destination port is stored in a cell header of the cells, sending the cells to the destination port via at least one switch fabric controller (SFC), receiving the cells at a fabric interface of an appliance DLC, reassembling the cells into a second packet, performing one or more services on the second packet using the appliance DLC, and sending the second packet to its intended port.

摘要翻译： 根据一个实施例，一种用于提供可伸缩虚拟设备云（SVAC）服务的方法包括使用至少一个交换分布式线卡（DLC）接收具有指向SVAC的多个分组的输入数据业务，确定分组满足条件 访问控制列表（ACL），根据满足ACL的条件指定发送分组的目的地端口，将分组分段成小区，其中指定的目的地端口存储在小区的小区头部中，将小区发送到 经由至少一个交换结构控制器（SFC）的目的地端口，在设备DLC的结构接口处接收小区，将小区重新组合成第二分组，使用设备DLC在第二分组上执行一个或多个服务，以及发送 第二个数据包到其预定端口。