公开(公告)号：US08473809B2

公开(公告)日：2013-06-25

申请号：US12839237

申请日：2010-07-19

申请人： Jun Wan ,  Alex Mak ,  Tien-Chien Kuo ,  Yan Li ,  Jian Chen

发明人： Jun Wan ,  Alex Mak ,  Tien-Chien Kuo ,  Yan Li ,  Jian Chen

IPC分类号： G06F11/00 ,  G11C29/00 ,  G11C7/00

CPC分类号： G11C11/5642 ,  G11C11/5628 ,  G11C29/00

摘要： Non-volatile storage devices and techniques for operating non-volatile storage are described herein. One embodiment includes accessing “n” pages of data to be programmed into a group of non-volatile storage elements. The “n” pages are mapped to a data state for each of the non-volatile storage elements based on a coding scheme that evenly distributes read errors across the “n” pages of data. Each of the non-volatile storage elements in the group are programmed to a threshold voltage range based on the data states to which the plurality of pages have been mapped. The programming may include programming the “n” pages simultaneously. In one embodiment, mapping the plurality of pages is based on a coding scheme that distributes a significant failure mode (for example, program disturb errors) to a first of the pages and a significant failure mode (for example, data retention errors) to a second of the pages.

摘要翻译： 本文描述了用于操作非易失性存储器的非易失性存储设备和技术。 一个实施例包括访问要编程到一组非易失性存储元件中的“n”页数据。 基于在“n”页数据上均匀分布读取错误的编码方案，将“n”个页映射到每个非易失性存储元件的数据状态。 基于已经映射了多个页面的数据状态，组中的每个非易失性存储元件被编程到阈值电压范围。 编程可以包括同时对“n”页进行编程。 在一个实施例中，映射多个页面是基于将显着的故障模式（例如，程序干扰错误）分配给第一页面的编码方案和将重大故障模式（例如，数据保留错误）分配给 第二页。

公开(公告)号：US07616499B2

公开(公告)日：2009-11-10

申请号：US11617541

申请日：2006-12-28

申请人： Jun Wan ,  Jeffrey W. Lutze ,  Jian Chen ,  Yan Li ,  Alex Mak

发明人： Jun Wan ,  Jeffrey W. Lutze ,  Jian Chen ,  Yan Li ,  Alex Mak

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/06

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621

摘要： Data verification in a memory device using a portion of a data retention margin is provided. A bit count is read from the region to determine whether errors will result in the memory. A read in one or more retention margin portions is performed after the normal program verify sequence and if the number of bits in these regions is more than a pre-set the memory will fail verify status. A method of verifying data in a memory device includes the steps of: defining an retention margin between adjacent data thresholds; programming the memory device with data; determining whether bits are present in the data retention margin; and if the number of bits in the retention margin exceeds a threshold, generating an error.

摘要翻译： 提供了使用部分数据保留余量的存储器件中的数据验证。 从区域读取位计数，以确定错误是否会导致内存。 在正常程序验证序列之后执行在一个或多个保留边缘部分中的读取，并且如果这些区域中的位数大于预设，则存储器将失败验证状态。 验证存储器件中的数据的方法包括以下步骤：定义相邻数据阈值之间的保留余量; 使用数据对存储设备进行编程; 确定位是否存在于数据保留余量中; 并且如果保留余量中的比特数超过阈值，则产生错误。

公开(公告)号：US07301816B2

公开(公告)日：2007-11-27

申请号：US11616762

申请日：2006-12-27

申请人： Yan Li ,  Jian Chen

发明人： Yan Li ,  Jian Chen

IPC分类号： G11C11/34

CPC分类号： G11C16/26 ,  G11C11/5642 ,  G11C16/3418 ,  G11C16/3422

摘要： Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). The problem occurs most pronouncedly between sets of adjacent memory cells that have been programmed at different times. To compensate for this coupling, the read process for a given memory cell will take into account the programmed state of an adjacent memory cell.

摘要翻译： 存在于非易失性存储单元的浮动栅极（或其他电荷存储元件）上的表观电荷的变化可能发生，因为基于存储在相邻浮动栅极（或其它相邻电荷存储元件）中的电荷的电场的耦合 ）。 在不同时间编程的相邻存储器单元组之间最明显地出现该问题。 为了补偿该耦合，给定存储器单元的读取过程将考虑相邻存储器单元的编程状态。

公开(公告)号：US20070109850A1

公开(公告)日：2007-05-17

申请号：US11616757

申请日：2006-12-27

申请人： Yan Li ,  Jian Chen

发明人： Yan Li ,  Jian Chen

IPC分类号： G11C16/04

CPC分类号： G11C16/26 ,  G11C11/5642 ,  G11C16/3418 ,  G11C16/3422

摘要： Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). The problem occurs most pronouncedly between sets of adjacent memory cells that have been programmed at different times. To compensate for this coupling, the read process for a given memory cell will take into account the programmed state of an adjacent memory cell.

公开(公告)号：US20070103987A1

公开(公告)日：2007-05-10

申请号：US11616762

申请日：2006-12-27

申请人： Yan Li ,  Jian Chen

发明人： Yan Li ,  Jian Chen

IPC分类号： G11C16/06 ,  G11C11/34

CPC分类号： G11C16/26 ,  G11C11/5642 ,  G11C16/3418 ,  G11C16/3422

摘要： Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). The problem occurs most pronouncedly between sets of adjacent memory cells that have been programmed at different times. To compensate for this coupling, the read process for a given memory cell will take into account the programmed state of an adjacent memory cell.

公开(公告)号：US20070103975A1

公开(公告)日：2007-05-10

申请号：US11616769

申请日：2006-12-27

申请人： Yan Li ,  Jian Chen

发明人： Yan Li ,  Jian Chen

IPC分类号： G11C16/04

CPC分类号： G11C16/26 ,  G11C11/5642 ,  G11C16/3418 ,  G11C16/3422

摘要： Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). The problem occurs most pronouncedly between sets of adjacent memory cells that have been programmed at different times. To compensate for this coupling, the read process for a given memory cell will take into account the programmed state of an adjacent memory cell.

公开(公告)号：US07046548B2

公开(公告)日：2006-05-16

申请号：US11055776

申请日：2005-02-09

申请人： Raul-Adrian Cernea ,  Khandker N. Quader ,  Yan Li ,  Jian Chen ,  Yupin Fong

发明人： Raul-Adrian Cernea ,  Khandker N. Quader ,  Yan Li ,  Jian Chen ,  Yupin Fong

IPC分类号： G11C16/04

CPC分类号： G11C16/3427 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/3418

摘要： Techniques of reducing erroneous readings of the apparent charge levels stored in a number of rows of memory cells on account of capacitive coupling between the cells. All pages of a first row are programmed with a first pass, followed by programming all pages of a second adjacent row with a first pass, after which the first row is programmed with a second pass, and then all pages of a third row are programmed with a first pass, followed by returning to program the second row with a second pass, and so on, in a back-and-forth manner across the rows of an array. This minimizes the effect on the apparent charge stored on rows of memory cells that can occur by later writing data into adjacent rows of memory cells.

摘要翻译： 考虑到电池之间的电容耦合，减少存储在多行存储器单元中的表观电荷水平的错误读数的技术。 第一行的所有页面都用第一遍编程，然后用第一遍编程第二相邻行的所有页面，之后第一行以第二遍编程，然后第三行的所有页面都被编程 第一遍，然后通过第二遍返回到第二行的程序，依次类推，跨越数组的行。 这最大程度地减少了通过稍后将数据写入存储器单元的相邻行中可能发生的对存储器单元行存储的视在电荷的影响。

公开(公告)号：US06975537B2

公开(公告)日：2005-12-13

申请号：US11049802

申请日：2005-02-03

申请人： Jeffrey W. Lutze ,  Jian Chen ,  Yan Li ,  Masaaki Higashitani

发明人： Jeffrey W. Lutze ,  Jian Chen ,  Yan Li ,  Masaaki Higashitani

IPC分类号： G11C11/34 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34

CPC分类号： G11C16/3418 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3454

摘要： A non-volatile semiconductor memory system (or other type of memory system) is programmed in a manner that avoids program disturb. In one embodiment that includes a flash memory system using a NAND architecture, program disturb is avoided by increasing the channel potential of the source side of the NAND string during the programming process. One exemplar implementation includes applying a voltage (e.g. Vdd) to the source contact and turning on the source side select transistor for the NAND sting corresponding to the cell being inhibited. Another implementation includes applying a pre-charging voltage to the unselected word lines of the NAND string corresponding to the cell being inhibited prior to applying the program voltage.

公开(公告)号：US06870768B2

公开(公告)日：2005-03-22

申请号：US10923320

申请日：2004-08-20

申请人： Raul-Adrian Cernea ,  Khandker N. Quader ,  Yan Li ,  Jian Chen ,  Yupin Fong

发明人： Raul-Adrian Cernea ,  Khandker N. Quader ,  Yan Li ,  Jian Chen ,  Yupin Fong

IPC分类号： G11C16/02 ,  G11C11/56 ,  G11C16/10 ,  G11C16/34 ,  G11C16/04

CPC分类号： G11C16/3427 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/3418

摘要： Techniques of reducing erroneous readings of the apparent charge levels stored in a number of rows of memory cells on account of capacitive coupling between the cells. All pages of a first row are programmed with a first pass, followed by programming all pages of a second adjacent row with a first pass, after which the first row is programmed with a second pass, and then all pages of a third row are programmed with a first pass, followed by returning to program the second row with a second pass, and so on, in a back-and-forth manner across the rows of an array. This minimizes the effect on the apparent charge stored on rows of memory cells that can occur by later writing data into adjacent rows of memory cells.

摘要翻译： 考虑到电池之间的电容耦合，减少存储在多行存储器单元中的表观电荷水平的错误读数的技术。 第一行的所有页面都用第一遍编程，然后用第一遍编程第二相邻行的所有页面，之后第一行以第二遍编程，然后第三行的所有页面都被编程 第一遍，然后通过第二遍返回到第二行的程序，依次类推，跨越数组的行。 这最大程度地减少了通过稍后将数据写入存储器单元的相邻行中可能发生的对存储器单元行存储的视在电荷的影响。

公开(公告)号：US20050018482A1

公开(公告)日：2005-01-27

申请号：US10923320

申请日：2004-08-20

申请人： Raul-Adrian Cemea ,  Khandker Quader ,  Yan Li ,  Jian Chen ,  Yupin Fong

发明人： Raul-Adrian Cemea ,  Khandker Quader ,  Yan Li ,  Jian Chen ,  Yupin Fong

IPC分类号： G11C16/02 ,  G11C11/56 ,  G11C16/10 ,  G11C16/34 ,  G11C11/34

CPC分类号： G11C16/3427 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/3418

摘要： Techniques of reducing erroneous readings of the apparent charge levels stored in a number of rows of memory cells on account of capacitive coupling between the cells. All pages of a first row are programmed with a first pass, followed by programming all pages of a second adjacent row with a first pass, after which the first row is programmed with a second pass, and then all pages of a third row are programmed with a first pass, followed by returning to program the second row with a second pass, and so on, in a back-and-forth manner across the rows of an array. This minimizes the effect on the apparent charge stored on rows of memory cells that can occur by later writing data into adjacent rows of memory cells.

摘要翻译： 考虑到电池之间的电容耦合，减少存储在多行存储器单元中的表观电荷水平的错误读数的技术。 第一行的所有页面都用第一遍编程，然后用第一遍编程第二相邻行的所有页面，之后第一行以第二遍编程，然后第三行的所有页面都被编程 第一遍，然后通过第二遍返回到第二行的程序，依次类推，跨越数组的行。 这最大程度地减少了通过稍后将数据写入存储器单元的相邻行中可能发生的对存储器单元行存储的视在电荷的影响。