公开(公告)号：US06504537B1

公开(公告)日：2003-01-07

申请号：US09655103

申请日：2000-09-05

申请人： Henry P. Moreton ,  Douglas H. Rogers

发明人： Henry P. Moreton ,  Douglas H. Rogers

IPC分类号： G06T1530

CPC分类号： G06T17/20

摘要： A system, method and article of manufacture are provided for decomposing surfaces for rendering purposes during computer graphics processing. Initially, an interior mesh of primitives is defined in a surface to be rendered. Next, a plurality of surrounding meshes is defined along sides of the interior mesh. The exterior sides of the surrounding meshes each include a plurality of equally sized segments and at least one fractional segment that is a fraction of the equally sized segments. With this configuration, a pattern of triangles is used that permits the number of triangles to be varied continuously from frame to frame while accommodating incremental evaluation techniques such as forward differencing without visual artifacts such as popping.

摘要翻译： 在计算机图形处理期间提供用于分解表面以用于呈现目的的系统，方法和制造品。 最初，原始图案的内部网格被定义在要渲染的表面中。 接下来，沿着内部网格的侧面限定多个周围的网格。 周围网格的外侧各自包括多个相同大小的段和至少一个小数段，其是相当大小的段的一部分。 使用这种配置，使用三角形图案，其允许三角形的数量从帧到帧连续变化，同时容纳诸如前向差分的增量评估技术，而不会出现诸如弹出的视觉伪影。

公开(公告)号：US5835133A

公开(公告)日：1998-11-10

申请号：US590347

申请日：1996-01-23

申请人： Henry P. Moreton ,  Bryan E. Loucks

发明人： Henry P. Moreton ,  Bryan E. Loucks

IPC分类号： G02B27/22 ,  G03B35/10 ,  H04N13/00 ,  H04N13/02

CPC分类号： G03B35/10 ,  G02B27/2264 ,  H04N13/0048 ,  H04N13/0217 ,  H04N13/0055 ,  H04N13/021 ,  H04N13/0221 ,  H04N13/0239 ,  H04N13/0285 ,  H04N13/0296 ,  H04N13/0434 ,  H04N13/0438 ,  H04N13/0497

摘要： A mechanism and method for recording stereo video with standard camera system electronics and a uniquely adapted optical assembly is disclosed. The optical assembly comprises left and right optical channels disposed to capture and project separate left and right images onto a single image sensor such that the boundary between the projected images is sharply delineated with no substantial overlap or gap. The viewpoints of the left and right optical channels are separated by a distance, d, such that the captured images are differentiated to produce a stereo image pair. By proper disposition of the left and right optical channels, stereo image pairs exhibiting full stereo overlap without keystone distortion are obtained. One image of the stereo pair is produced for visualization by the left eye and the other image is produced for visualization by the right eye. Alternatively, the images can be interrogated by a computer system for generating three dimensional position data. The image sensor is scanned in a standard fashion such that the left and right images are sampled by the video sampling circuitry of the camera unit at substantially the same time. In one mode, a pair of anamorphic lenses compress the left and right images along the axis of the image sensor scan lines so that each video field represents a stereo pair of images at a substantially unity anamorphic ratio and at an aspect ratio substantially equal to that of the image sensor. In a another mode, a conventional (non-distorting) lens is utilized and each video frame represents a pair of images having an aspect ratio equal to one-half that of the image sensor. A stereo playback mechanism and method is also disclosed.

摘要翻译： 公开了一种使用标准摄像机系统电子装置记录立体视频和独特适用的光学组件的机构和方法。 光学组件包括左和右光学通道，其被设置成捕获并将分离的左和右图像投影到单个图像传感器上，使得投影图像之间的边界被清楚地描绘而没有实质的重叠或间隙。 左和右光学通道的视点被分开距离d，使得捕获的图像被区分以产生立体图像对。 通过适当地设置左右光通道，可以获得没有梯形失真的完全立体重叠的立体图像对。 立体声对的一个图像被产生用于由左眼进行可视化，并且另一图像被产生用于通过右眼可视化。 或者，可以由用于产生三维位置数据的计算机系统询问图像。 以标准方式扫描图像传感器，使得左右图像基本上同时由相机单元的视频采样电路采样。 在一种模式中，一对变形透镜沿着图像传感器扫描线的轴压缩左图像和右图像，使得每个视频场以基本上一致的变形比表示立体图像，并且基本上与 的图像传感器。 在另一种模式中，使用常规（非失真）透镜，并且每个视频帧表示具有等于图像传感器的一半的宽高比的一对图像。 还公开了立体声播放机构和方法。

公开(公告)号：US09013498B1

公开(公告)日：2015-04-21

申请号：US12340499

申请日：2008-12-19

申请人： John S. Montrym ,  Andrew J. Tao ,  Henry P. Moreton ,  Emmett M. Kilgariff ,  Cass W. Everitt ,  Alexander L. Minkin ,  Eric Anderson ,  Yan Yan Tang ,  Jerome F. Duluk, Jr.

发明人： John S. Montrym ,  Andrew J. Tao ,  Henry P. Moreton ,  Emmett M. Kilgariff ,  Cass W. Everitt ,  Alexander L. Minkin ,  Eric Anderson ,  Yan Yan Tang ,  Jerome F. Duluk, Jr.

IPC分类号： G09G5/00 ,  G09G5/37

CPC分类号： G09G5/37 ,  G06T15/005 ,  G06T15/04 ,  G06T2210/36

摘要： A system and method for tracking and reporting texture map levels of detail that are computed during graphics processing allows for efficient management of texture map storage. Minimum and/or maximum pre-clamped texture map levels of detail values are tracked by a graphics processor and an array stored in memory is updated to report the minimum and/or maximum values for use by an application program. The minimum and/or maximum values may be used to determine the active set of texture map levels of detail that is loaded into graphics memory.

摘要翻译： 用于跟踪和报告在图形处理期间计算的细节纹理图层级的系统和方法允许纹理图存储的有效管理。 图形处理器跟踪细节值的最小和/或最大预夹紧纹理映射级别，更新存储在存储器中的阵列以报告应用程序使用的最小值和/或最大值。 最小值和/或最大值可用于确定加载到图形存储器中的细节的纹理映射级别的活动集合。

公开(公告)号：US20120284568A1

公开(公告)日：2012-11-08

申请号：US13550468

申请日：2012-07-16

申请人： Jerome F. Duluk, JR. ,  Henry P. Moreton ,  Steven E. Molnar ,  John S. Montrym

发明人： Jerome F. Duluk, JR. ,  Henry P. Moreton ,  Steven E. Molnar ,  John S. Montrym

IPC分类号： G06F11/30

CPC分类号： G06F11/0793 ,  G06F11/0715 ,  G06F11/0751

摘要： A method and system for overriding state information programmed into a processor using an application programming interface (API) avoids introducing error conditions in the processor. An override monitor unit within the processor stores the programmed state for any setting that is overridden so that the programmed state can be restored when the error condition no longer exists. The override monitor unit overrides the programmed state by forcing the setting to a legal value that does not cause an error condition. The processor is able to continue operating without notifying a device driver that an error condition has occurred since the error condition is avoided.

摘要翻译： 使用应用编程接口（API）将编程到处理器中的状态信息进行覆盖的方法和系统避免了在处理器中引入错误状况。 处理器内的覆盖监视单元存储被覆盖的任何设置的编程状态，以便当错误条件不再存在时可以恢复编程状态。 覆盖监视器单元通过强制设置为不引起错误条件的合法值来覆盖编程状态。 处理器能够在不通知设备驱动程序的情况下继续运行，因为避免了错误条件，所以发生了错误状况。

公开(公告)号：US08074058B2

公开(公告)日：2011-12-06

申请号：US12480414

申请日：2009-06-08

申请人： Timothy J. Van Hook ,  Peter Hsu ,  William A. Huffman ,  Henry P. Moreton ,  Earl A. Killian

发明人： Timothy J. Van Hook ,  Peter Hsu ,  William A. Huffman ,  Henry P. Moreton ,  Earl A. Killian

IPC分类号： G06F15/00

CPC分类号： G06F9/30014 ,  G06F9/30025 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/3885 ,  G06F9/3887 ,  G06F15/8084

摘要： The present invention provides extended precision in SIMD arithmetic operations in a processor having a register file and an accumulator. A first set of data elements and a second set of data elements are loaded into first and second vector registers, respectively. Each data element comprises N bits. Next, an arithmetic instruction is fetched from memory. The arithmetic instruction is decoded. Then, the first vector register and the second vector register are read from the register file. The present invention executes the arithmetic instruction on corresponding data elements in the first and second vector registers. The resulting element of the execution is then written into the accumulator. Then, the resulting element is transformed into an N-bit width element and written into a third register for further operation or storage in memory. The transformation of the resulting element can include, for example, rounding, clamping, and/or shifting the element.

摘要翻译： 本发明在具有寄存器文件和累加器的处理器中提供SIMD算术运算的扩展精度。 第一组数据元素和第二组数据元素分别被加载到第一和第二向量寄存器中。 每个数据元素包括N位。 接下来，从存储器中取出算术指令。 算术指令被解码。 然后，从寄存器文件读取第一向量寄存器和第二向量寄存器。 本发明对第一和第二向量寄存器中的相应数据元素执行算术指令。 然后将执行的结果元素写入累加器。 然后，将所得到的元素变换为N位元素，并写入第三寄存器以进一步操作或存储在存储器中。 所得到的元件的变换可以包括例如舍入，夹紧和/或移动元件。

公开(公告)号：US07880747B1

公开(公告)日：2011-02-01

申请号：US11610127

申请日：2006-12-13

申请人： Steven E. Molnar ,  Jerome F. Duluk, Jr. ,  Henry P. Moreton ,  Daniel P. Wilde ,  Mark J. French ,  Bengt-Olaf Schneider ,  Jonathan J. Dunaisky ,  Weizhong Xu

发明人： Steven E. Molnar ,  Jerome F. Duluk, Jr. ,  Henry P. Moreton ,  Daniel P. Wilde ,  Mark J. French ,  Bengt-Olaf Schneider ,  Jonathan J. Dunaisky ,  Weizhong Xu

IPC分类号： G09G5/02

CPC分类号： G06T11/40 ,  G06T15/005 ,  G06T15/50 ,  G09G5/02

摘要： A technique for handling floating-point special values, e.g., Infinity, NaN, −Zero, and denorms, during blend operations is provided so that blend operations on fragment color values that contain special values can be performed in compliance with special value handling rules. In particular, the presence of special values is detected or the potential presence of special values is detected. This information is used to qualify when blend optimizations may be performed, so that floating point blend operations can remain conformant to special value handling rules.

摘要翻译： 提供了一种在混合操作期间处理浮点特殊值的技术，例如Infinity，NaN，-Zero和denorms，以便可以根据特殊值处理规则执行对包含特殊值的片段颜色值的混合操作。 特别地，检测到特殊值的存在或者检测到特殊值的潜在存在。 此信息用于限定可以执行混合优化时，以便浮点混合操作可以保持符合特殊值处理规则。

公开(公告)号：US07739556B1

公开(公告)日：2010-06-15

申请号：US11934686

申请日：2007-11-02

申请人： Jerome F. Duluk, Jr. ,  Henry P. Moreton ,  John S. Montrym ,  Nathaniel C. Voorhies

发明人： Jerome F. Duluk, Jr. ,  Henry P. Moreton ,  John S. Montrym ,  Nathaniel C. Voorhies

IPC分类号： G06F11/00

CPC分类号： G06F11/0793 ,  G06F11/0715 ,  G06F11/0751

摘要： A method and system for overriding state information programmed into a processor using an application programming interface (API) avoids introducing error conditions in the processor. An override monitor unit within the processor stores the programmed state for any setting that is overridden so that the programmed state can be restored when the error condition no longer exists. The override monitor unit overrides the programmed state by forcing the setting to a legal value that does not cause an error condition. The processor is able to continue operating without notifying a device driver that an error condition has occurred since the error condition is avoided.

摘要翻译： 使用应用编程接口（API）将编程到处理器中的状态信息进行覆盖的方法和系统避免了在处理器中引入错误状况。 处理器内的覆盖监视单元存储被覆盖的任何设置的编程状态，以便当错误条件不再存在时可以恢复编程状态。 覆盖监视器单元通过强制设置为不引起错误条件的合法值来覆盖编程状态。 处理器能够在不通知设备驱动程序的情况下继续运行，因为避免了错误条件，所以发生了错误状况。

公开(公告)号：US20090249039A1

公开(公告)日：2009-10-01

申请号：US12480414

申请日：2009-06-08

申请人： Timothy Van Hook ,  Peter Hsu ,  William A. Huffman ,  Henry P. Moreton ,  Earl A. Killian

发明人： Timothy Van Hook ,  Peter Hsu ,  William A. Huffman ,  Henry P. Moreton ,  Earl A. Killian

IPC分类号： G06F9/302

CPC分类号： G06F9/30014 ,  G06F9/30025 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/3885 ,  G06F9/3887 ,  G06F15/8084

摘要： The present invention provides extended precision in SIMD arithmetic operations in a processor having a register file and an accumulator. A first set of data elements and a second set of data elements are loaded into first and second vector registers, respectively. Each data element comprises N bits. Next, an arithmetic instruction is fetched from memory. The arithmetic instruction is decoded. Then, the first vector register and the second vector register are read from the register file. The present invention executes the arithmetic instruction on corresponding data elements in the first and second vector registers. The resulting element of the execution is then written into the accumulator. Then, the resulting element is transformed into an N-bit width element and written into a third register for further operation or storage in memory. The transformation of the resulting element can include, for example, rounding, clamping, and/or shifting the element.

摘要翻译： 本发明在具有寄存器文件和累加器的处理器中提供SIMD算术运算的扩展精度。 第一组数据元素和第二组数据元素分别被加载到第一和第二向量寄存器中。 每个数据元素包括N位。 接下来，从存储器中取出算术指令。 算术指令被解码。 然后，从寄存器文件读取第一向量寄存器和第二向量寄存器。 本发明对第一和第二向量寄存器中的相应数据元素执行算术指令。 然后将执行的结果元素写入累加器。 然后，将所得到的元素变换为N位元素，并写入第三寄存器以进一步操作或存储在存储器中。 所得到的元件的变换可以包括例如舍入，夹紧和/或移动元件。

公开(公告)号：US07546443B2

公开(公告)日：2009-06-09

申请号：US11337440

申请日：2006-01-24

申请人： Timothy J. Van Hook ,  Peter Hsu ,  William A. Huffman ,  Henry P. Moreton ,  Earl A. Killian

发明人： Timothy J. Van Hook ,  Peter Hsu ,  William A. Huffman ,  Henry P. Moreton ,  Earl A. Killian

IPC分类号： G06F15/00

CPC分类号： G06F9/30014 ,  G06F9/30025 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/3885 ,  G06F9/3887 ,  G06F15/8084

摘要： The present invention provides extended precision in SIMD arithmetic operations in a processor having a register file and an accumulator. A first set of data elements and a second set of data elements are loaded into first and second vector registers, respectively. Each data element comprises N bits. Next, an arithmetic instruction is fetched from memory. The arithmetic instruction is decoded. Then, the first vector register and the second vector register are read from the register file. The present invention executes the arithmetic instruction on corresponding data elements in the first and second vector registers. The resulting element of the execution is then written into the accumulator. Then, the resulting element is transformed into an N-bit width element and written into a third register for further operation or storage in memory. The transformation of the resulting element can include, for example, rounding, clamping, and/or shifting the element.

摘要翻译： 本发明在具有寄存器文件和累加器的处理器中提供SIMD算术运算的扩展精度。 第一组数据元素和第二组数据元素分别被加载到第一和第二向量寄存器中。 每个数据元素包括N位。 接下来，从存储器中取出算术指令。 算术指令被解码。 然后，从寄存器文件读取第一向量寄存器和第二向量寄存器。 本发明对第一和第二向量寄存器中的相应数据元素执行算术指令。 然后将执行的结果元素写入累加器。 然后，将所得到的元素变换为N位元素，并写入第三寄存器以进一步操作或存储在存储器中。 所得到的元件的变换可以包括例如舍入，夹紧和/或移动元件。

公开(公告)号：US07233335B2

公开(公告)日：2007-06-19

申请号：US10419524

申请日：2003-04-21

申请人： Henry P. Moreton ,  John Erik Lindholm ,  Matthew N. Papakipos ,  Rui M. Bastos

发明人： Henry P. Moreton ,  John Erik Lindholm ,  Matthew N. Papakipos ,  Rui M. Bastos

IPC分类号： G06T1/00 ,  G06F13/18 ,  G06F12/02 ,  G09G5/399

CPC分类号： G06T1/60

摘要： System and method for reserving a memory space for multithreaded processing is described. Memory space within a memory resource is allocated responsive to thread type. Examples of thread types for graphics processing include primitive, vertex and pixel types. Memory space allocated may be of a predetermined size for a thread type. Memory locations within a first memory space may be interleaved with memory locations within a second memory space.

摘要翻译： 描述用于预留用于多线程处理的存储空间的系统和方法。 响应于线程类型分配内存资源内的内存空间。 用于图形处理的线程类型的示例包括原始，顶点和像素类型。 分配的内存空间可以是线程类型的预定大小。 第一存储器空间内的存储器位置可以与第二存储器空间内的存储器位置交错。