Polypyrrole and silver vanadium oxide composite
    51.
    发明授权
    Polypyrrole and silver vanadium oxide composite 有权
    聚吡咯和银氧化钒复合材料

    公开(公告)号:US08398951B2

    公开(公告)日:2013-03-19

    申请号:US13411976

    申请日:2012-03-05

    IPC分类号: H01M4/02

    摘要: In one embodiment of the present disclosure, a composite electrode for a battery is provided. The composite electrode includes silver vanadium oxide present in an amount from about 75 weight percent to about 99 weight percent and polypyrrole present in an amount from about 1 weight percent to about 25 weight percent.

    摘要翻译: 在本公开的一个实施例中,提供了一种用于电池的复合电极。 复合电极包括以约75重量%至约99重量%的量存在的银钒氧化物,并且存在量为约1重量%至约25重量%的聚吡咯。

    DISPOSABLE LIFE-SAVING GARMENT
    52.
    发明申请
    DISPOSABLE LIFE-SAVING GARMENT 有权
    可弃置的救生衣

    公开(公告)号:US20120174297A1

    公开(公告)日:2012-07-12

    申请号:US13386127

    申请日:2010-07-01

    申请人: Jong-Won Lee

    发明人: Jong-Won Lee

    IPC分类号: A62B17/00

    摘要: A disposable life-saving garment for use in the event of fire, comprises a body-protecting portion and a head-protecting portion. The body-protecting portion is configured with a lining formed to enclose the body of a wearer and a cover covering the liner, the cover being made of a sealed material that can block the passage of air. A closed air passage is formed between the liner and cover. A compressed air tank installed in a pocket of the cover and is connected to the air passage through a check valve. An intake hose supplies compressed air from the air passage of the body-protecting portion to the head-protecting portion. The head-protecting portion has a heat-resistant transparent window and a one-way outlet unit. The body-protecting portion and the head-protecting portion are made of a nonflammable material or a fire retardant material.

    摘要翻译: 用于发生火灾的一次性救生衣包括身体保护部分和头部保护部分。 身体保护部分构造有衬里,该衬里形成为围绕穿着者的身体和覆盖衬里的罩,该罩由可阻挡空气通过的密封材料制成。 在衬套和盖子之间形成封闭的空气通道。 安装在盖的袋中的压缩空气罐,并通过止回阀与空气通道连接。 进气软管将压缩空气从身体保护部分的空气通道提供到头部保护部分。 头部保护部分具有耐热透明窗口和单向出口单元。 身体保护部分和头部保护部分由不燃材料或阻燃材料制成。

    Semiconductor integrated circuit with multi test
    54.
    发明授权
    Semiconductor integrated circuit with multi test 失效
    半导体集成电路多测试

    公开(公告)号:US08045408B2

    公开(公告)日:2011-10-25

    申请号:US12363338

    申请日:2009-01-30

    IPC分类号: G11C7/00 G11C8/00 G11C29/00

    摘要: A semiconductor integrated circuit includes a multi-mode control signal generating unit configured to control an activation of a up/down mat I/O switch control signal, which controls I/O switches in a up/down mat, according to a multi-test mode signal and a read/write discriminating signal, a multi-mode decoder configured to output multi-mat select signals to simultaneously activate a plurality of mats according to a multi-test mode active write signal, and a mat controller configured to enable word lines and the I/O switches according to the up/down mat I/O switch control signal and the multi-mat select signals.

    摘要翻译: 半导体集成电路包括:多模控制信号生成单元,被配置为根据多重测试来控制上/下按钮I / O开关控制信号的激活,其控制上/下垫中的I / O开关 模式信号和读/写鉴别信号;多模式解码器,被配置为输出多个席选择信号,以根据多测试模式有效写入信号同时激活多个地址;以及矩阵控制器,被配置为使得字线 和I / O开关根据上/下垫I / O开关控制信号和多功能选择信号。

    Scanning conversion apparatus and method
    55.
    发明授权
    Scanning conversion apparatus and method 失效
    扫描转换装置和方法

    公开(公告)号:US07791672B2

    公开(公告)日:2010-09-07

    申请号:US10811993

    申请日:2004-03-30

    IPC分类号: H04N11/20

    摘要: In the scanning conversion apparatus, interlaced-to-progressive scanning is performed according to one of at least two different techniques. The technique used depends on the interlaced scan data being converted. As examples, a spatial interpolation technique, a spatial/temporal interpolation technique, or other technique may be selected.

    摘要翻译: 在扫描转换装置中,根据至少两种不同的技术之一进行隔行扫描。 所使用的技术取决于被转换的隔行扫描数据。 作为示例,可以选择空间插值技术,空间/时间插值技术或其他技术。

    Semiconductor memory device
    56.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号:US07545687B2

    公开(公告)日:2009-06-09

    申请号:US11824423

    申请日:2007-06-29

    IPC分类号: G11C7/00

    摘要: A semiconductor memory device checks a RAS timing to recognize and set an operation timing of the semiconductor memory device. The semiconductor memory device includes an input buffer, a RAS timing controller and a bank controller. The input buffer transmits a RAS timing test signal. The RAS timing controller generates a RAS timing signal. The bank controller controls a refresh operation timing in response to an output of the input buffer in a test mode and the RAS timing signal in a normal mode.

    摘要翻译: 半导体存储器件检查RAS定时以识别并设置半导体存储器件的操作定时。 半导体存储器件包括输入缓冲器,RAS定时控制器和存储体控制器。 输入缓冲器发送RAS定时测试信号。 RAS定时控制器产生RAS定时信号。 银行控制器响应于测试模式下的输入缓冲器的输出和正常模式下的RAS定时信号来控制刷新操作定时。

    Refresh control circuit and method thereof and bank address signal change circuit and methods thereof
    58.
    发明授权
    Refresh control circuit and method thereof and bank address signal change circuit and methods thereof 有权
    刷新控制电路及其方法及其地址信号变换电路及其方法

    公开(公告)号:US07474578B2

    公开(公告)日:2009-01-06

    申请号:US11332477

    申请日:2006-01-17

    IPC分类号: G11C7/00 G11C8/00

    摘要: A refresh control circuit and method thereof and a bank address signal change circuit and methods thereof. The bank address signal change circuit may receive bank address signals from a bank address signal generation circuit. The received bank address signals may designate a first at least one of a plurality of memory banks. The bank address signal change circuit may determine whether the first at least one designated memory bank is associated with the longest refresh cycles from among the plurality of memory banks. Based on the determination, the bank address signal change circuit may generate a plurality of bank address signal change signals designating a second at least one of the plurality of memory banks. A refresh operation circuit may perform a refreshing operation on the second at least one memory banks in accordance with the bank address signal change signals. The bank address signal generation circuit, bank address signal change circuit and refresh operation circuit may each be included in a refresh control circuit.

    摘要翻译: 一种刷新控制电路及其方法及其地址信号变换电路及其方法。 银行地址信号变换电路可以从存储体地址信号发生电路接收存储体地址信号。 所接收的存储体地址信号可以指定多个存储体中的第一至少一个。 银行地址信号变化电路可以确定第一至少一个指定的存储体是否与多个存储体中的最长刷新周期相关联。 基于该确定,存储体地址信号改变电路可以产生指定多个存储体中的第二至少一个的多个存储体地址信号改变信号。 刷新操作电路可以根据存储体地址信号改变信号对第二至少一个存储体执行刷新操作。 存储体地址信号发生电路,存储体地址信号改变电路和刷新操作电路可以各自包括在刷新控制电路中。

    Wordline enable circuit in semiconductor memory device and method thereof
    60.
    发明授权
    Wordline enable circuit in semiconductor memory device and method thereof 有权
    半导体存储器件中的字线使能电路及其方法

    公开(公告)号:US07274619B2

    公开(公告)日:2007-09-25

    申请号:US11320967

    申请日:2005-12-30

    IPC分类号: G11C8/00

    摘要: There is provided a wordline enable circuit and its method for reducing power consumption by controlling a wordline select signal in a self-refresh mode. The wordline enable circuit includes a wordline control signal generating unit for outputting an untoggled wordline control signal while a unit wordline block is enabled in a self-refresh mode; a wordline enable signal generating unit for generating a wordline enable control signal, controlled by the untoggled wordline control signal and a toggled address signal, and a first to an n-th wordline enable power supply signals; and a wordline block enable unit for enabling each wordline, controlled by the wordline enable control signal and the first to the n-th wordline enable power supply signals.

    摘要翻译: 提供了一种字线使能电路及其通过在自刷新模式中控制字线选择信号来降低功耗的方法。 字线使能电路包括字线控制信号生成单元,用于在自刷新模式下启用单位字线块时输出未切换的字线控制信号; 字线使能信号生成单元,用于生成由未切换的字线控制信号和切换的地址信号控制的字线使能控制信号,以及第一至第n字线使能电源信号; 以及字线块使能单元,用于启用由字线使能控制信号和第一至第n字线使能电源信号控制的每个字线。