公开(公告)号：US5796133A

公开(公告)日：1998-08-18

申请号：US782827

申请日：1997-01-13

申请人： Kee-Won Kwon ,  Chang-Seok Kang

发明人： Kee-Won Kwon ,  Chang-Seok Kang

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11502 ,  H01L27/10808 ,  H01L27/10852 ,  H01L28/55 ,  H01L28/60

摘要： In a semiconductor device having a ferroelectric capacitor and manufacturing method thereof, a spacer comprising a low dielectric material is formed on the side surfaces of a plurality of lower electrodes separated into each cell unit, and a ferroelectric film is formed on the lower electrodes whereon the low dielectric material spacer is formed, and an upper electrode is formed on the ferroelectric film, to thereby prevent an error which may be caused between the adjacent lower electrodes.

摘要翻译： 在具有铁电电容器的半导体器件及其制造方法中，在分离成各单元的多个下电极的侧面形成有包含低电介质材料的间隔物，在下电极上形成强电介质膜， 形成低电介质材料隔离物，并且在铁电体膜上形成上电极，从而防止在相邻的下电极之间可能引起的误差。

公开(公告)号：US20080096328A1

公开(公告)日：2008-04-24

申请号：US11646217

申请日：2006-12-27

申请人： Jung-Dal Chol ,  Jong-Sun Sel ,  Chang-Seok Kang

发明人： Jung-Dal Chol ,  Jong-Sun Sel ,  Chang-Seok Kang

IPC分类号： H01L21/8232

CPC分类号： H01L21/823462 ,  H01L21/823456 ,  H01L21/823475 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11546 ,  Y10S257/903

摘要： A memory device includes a substrate having a cell region, a low voltage region and a high voltage region. A ground selection transistor, a string selection transistor and a cell transistor are in the cell region, a low voltage transistor is in the low voltage region, and a high voltage transistor is in the high voltage region. A common source contact is on the ground selection transistor and a low voltage contact is on the low voltage transistor. A bit line contact is on the string selection transistor, a high voltage contact is on the high voltage transistor, and a bit line is on the bit line contact. A first insulating layer is on the substrate, and a second insulating layer is on the first insulating layer. The common source contact and the first low voltage contact extend to a height of the first insulating layer, and the bit line contact and the first high voltage contact extend to a height of the second insulating layer.

摘要翻译： 存储器件包括具有单元区域，低电压区域和高电压区域的衬底。 接地选择晶体管，串选择晶体管和单元晶体管在单元区域中，低电压晶体管处于低电压区域，高压晶体管处于高电压区域。 公共源触点位于接地选择晶体管上，低压触点位于低压晶体管上。 串行选择晶体管上有一个位线接点，高电压晶体管上有高压触点，位线接触位线。 第一绝缘层在基板上，第二绝缘层位于第一绝缘层上。 共源极接触和第一低电压接触延伸到第一绝缘层的高度，并且位线接触和第一高电压接触延伸到第二绝缘层的高度。

公开(公告)号：US07012840B2

公开(公告)日：2006-03-14

申请号：US10874742

申请日：2004-06-24

申请人： Chang-Seok Kang

发明人： Chang-Seok Kang

IPC分类号： G11C7/00

CPC分类号： G11C5/147

摘要： The present invention relates to a semiconductor memory device having a voltage driving circuit. The semiconductor memory device includes: a core voltage node; a first driving unit having a first controller for comparing a feedback voltage level of the core voltage node with a reference voltage to output a first control signal, and a first pull-up driver for pulling up the core voltage node; a second driving unit having a second controller driven in response to the active signal as an enable signal to compare the feedback voltage level of the core voltage node with the reference voltage to output a second control signal, and a second pull-up driver for pulling up the core voltage node; and a selecting unit for selectively outputting the first control signal and the second control signal in response to the active signal as a select signal, in which the first pull-up driver is driven in response to the first control signal and the second pull-up driver is driven in response to an output signal of the selecting means.

摘要翻译： 本发明涉及具有电压驱动电路的半导体存储器件。 半导体存储器件包括：核心电压节点; 第一驱动单元，具有用于将核心电压节点的反馈电压电平与参考电压进行比较的第一控制器，以输出第一控制信号;以及第一上拉驱动器，用于提升所述核心电压节点; 第二驱动单元，具有响应于所述有源信号而被驱动的第二控制器作为使能信号，以将所述核心电压节点的反馈电压电平与所述参考电压进行比较以输出第二控制信号;以及第二上拉驱动器，用于拉 核心电压节点; 以及选择单元，用于响应于所述有效信号选择性地输出所述第一控制信号和所述第二控制信号作为选择信号，其中响应于所述第一控制信号和所述第二上拉驱动所述第一上拉驱动器 响应于选择装置的输出信号驱动驱动器。

公开(公告)号：US07002857B2

公开(公告)日：2006-02-21

申请号：US10879339

申请日：2004-06-28

申请人： Chang-Seok Kang

发明人： Chang-Seok Kang

IPC分类号： G11C7/00

CPC分类号： G11C7/227 ,  G11C7/06 ,  G11C7/22 ,  G11C11/4076

摘要： An automatic controlled delay circuit for use in a semiconductor memory device capable of detecting and adjusting a variation in delay with PVT variation delays a wordline activating signal by a predetermined time period and outputs the same as a bitline sense amplifier activating signal. The delay circuit is implemented with a plurality of delay blocks that are connected serially. The semiconductor device comprises a delay pulse signal generating block for generating a plurality of delayed pulse signals, each of which has different delay values at a time point at which the wordline activating signal is activated using an internal clock; a signal detecting block for detecting an activation time point of the bitline sense amplifier activating signal to generate a detected pulse signal; and a delay amount adjusting block for comparing the plurality of delayed pulse signals with the detected pulse signal to control the plurality of delay blocks.

摘要翻译： 用于能够检测和调整PVT变化的延迟变化的半导体存储器件中的自动控制延迟电路将字线激活信号延迟预定的时间周期，并将其作为位线读出放大器激活信号输出。 延迟电路由串联连接的多个延迟块来实现。 半导体器件包括用于产生多个延迟脉冲信号的延迟脉冲信号产生块，每个延迟脉冲信号在使用内部时钟激活字线激活信号的时间点具有不同的延迟值; 信号检测块，用于检测位线读出放大器激活信号的激活时间点以产生检测到的脉冲信号; 以及延迟量调整块，用于将所述多个延迟脉冲信号与所检测的脉冲信号进行比较，以控制所述多个延迟块。

公开(公告)号：US20050141288A1

公开(公告)日：2005-06-30

申请号：US10874742

申请日：2004-06-24

申请人： Chang-Seok Kang

发明人： Chang-Seok Kang

IPC分类号： G11C5/00 ,  G11C5/14

CPC分类号： G11C5/147

摘要： The present invention relates to a semiconductor memory device having a voltage driving circuit. The semiconductor memory device includes: a core voltage node; a first driving unit having a first controller for comparing a feedback voltage level of the core voltage node with a reference voltage to output a first control signal, and a first pull-up driver for pulling up the core voltage node; a second driving unit having a second controller driven in response to the active signal as an enable signal to compare the feedback voltage level of the core voltage node with the reference voltage to output a second control signal, and a second pull-up driver for pulling up the core voltage node; and a selecting unit for selectively outputting the first control signal and the second control signal in response to the active signal as a select signal, in which the first pull-up driver is driven in response to the first control signal and the second pull-up driver is driven in response to an output signal of the selecting means.

摘要翻译： 本发明涉及具有电压驱动电路的半导体存储器件。 半导体存储器件包括：核心电压节点; 第一驱动单元，具有用于将核心电压节点的反馈电压电平与参考电压进行比较的第一控制器，以输出第一控制信号;以及第一上拉驱动器，用于提升所述核心电压节点; 第二驱动单元，具有响应于所述有源信号而被驱动的第二控制器作为使能信号，以将所述核心电压节点的反馈电压电平与所述参考电压进行比较以输出第二控制信号;以及第二上拉驱动器，用于拉 核心电压节点; 以及选择单元，用于响应于所述有效信号选择性地输出所述第一控制信号和所述第二控制信号作为选择信号，其中响应于所述第一控制信号和所述第二上拉驱动所述第一上拉驱动器 响应于选择装置的输出信号驱动驱动器。