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    VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME
    1.
    发明申请
    VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 审中-公开
    垂直存储器件及其制造方法

    公开(公告)号：US20150060979A1

    公开(公告)日：2015-03-05

    申请号：US14471619

    申请日：2014-08-28

    申请人： Gil-Sung Lee ,  Chang-Seok Kang ,  Ju-Hyung Kim

    发明人： Gil-Sung Lee ,  Chang-Seok Kang ,  Ju-Hyung Kim

    IPC分类号： H01L27/115 ,  H01L29/10 ,  H01L29/423

    CPC分类号： H01L27/11582 ,  H01L27/1157 ,  H01L29/105 ,  H01L29/42356

    摘要： A vertical memory device includes a channel and gate electrodes. The channel extends in a vertical direction with respect to a top surface of a substrate. The gate electrodes are disposed on an outer sidewall of the channel. The gate electrodes includes a ground selection line (GSL), a word line, a string selection line (SSL) and a first dummy word line sequentially stacked from the top surface of the substrate in the vertical direction to be spaced apart from each other. The channel includes an impurity region at a portion adjacent to the SSL.

    摘要翻译： 垂直存储器件包括沟道和栅电极。 通道相对于基板的顶表面在垂直方向上延伸。 栅电极设置在通道的外侧壁上。 栅极电极包括从基板的上表面沿垂直方向依次堆叠的接地选择线（GSL），字线，串选择线（SSL）和第一虚拟字线，以彼此间隔开。 该通道在与SSL相邻的部分包括杂质区域。

    NONVOLATILE MEMORY DEVICE AND FABRICATING METHOD THEREOF
    2.
    发明申请
    NONVOLATILE MEMORY DEVICE AND FABRICATING METHOD THEREOF 有权
    非易失性存储器件及其制造方法

    公开(公告)号：US20130228849A1

    公开(公告)日：2013-09-05

    申请号：US13775833

    申请日：2013-02-25

    申请人： Ju-Hyung Kim ,  Chang-Seok Kang ,  Woon-Kyung Lee

    发明人： Ju-Hyung Kim ,  Chang-Seok Kang ,  Woon-Kyung Lee

    IPC分类号： H01L29/792 ,  H01L29/66

    CPC分类号： H01L29/792 ,  H01L27/11582 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/66833 ,  H01L29/7926

    摘要： A nonvolatile memory device comprises a channel pattern, a first interlayer dielectric film and a second interlayer dielectric film spaced apart from each other and stacked over each other, a gate pattern disposed between the first interlayer dielectric film and the second interlayer dielectric film, a trap layer disposed between the gate pattern and the channel pattern and a charge spreading inhibition layer disposed between the channel pattern and the first interlayer dielectric film and between the channel pattern and the second interlayer dielectric film. The charge spreading inhibition layer may include charges inside or on its surface. The charge spreading inhibition layer includes at least one of a metal oxide film or a metal nitride film or a metal oxynitride film having a greater dielectric constant than a silicon oxide film.

    摘要翻译： 非易失性存储器件包括彼此间隔开并且彼此堆叠的沟道图案，第一层间电介质膜和第二层间电介质膜，布置在第一层间电介质膜和第二层间电介质膜之间的栅极图案，阱 设置在栅极图案和沟道图案之间的层，以及设置在沟道图案和第一层间电介质膜之间以及沟道图案和第二层间电介质膜之间的电荷扩展抑制层。 电荷扩散抑制层可以包括其表面内部或其表面上的电荷。 电荷扩散抑制层包括金属氧化物膜或金属氮化物膜或具有比氧化硅膜更大的介电常数的金属氧氮化物膜中的至少一种。

    Charge-trap nonvolatile memory devices
    6.
    发明授权
    Charge-trap nonvolatile memory devices 有权
    充电陷阱非易失性存储器件

    公开(公告)号：US07772639B2

    公开(公告)日：2010-08-10

    申请号：US11700315

    申请日：2007-01-31

    申请人： Chang-Seok Kang ,  Jung-Dal Choi ,  Ju-Hyung Kim ,  Jong-Sun Sel ,  Jae-Sung Sim ,  Sang-Hun Jeon

    发明人： Chang-Seok Kang ,  Jung-Dal Choi ,  Ju-Hyung Kim ,  Jong-Sun Sel ,  Jae-Sung Sim ,  Sang-Hun Jeon

    IPC分类号： H01L29/788

    CPC分类号： H01L27/11568 ,  H01L27/115

    摘要： Nonvolatile memory devices including device isolation patterns on a semiconductor substrate are provided. The device isolation patterns define a cell active region and a peripheral active region of the semiconductor substrate. Cell gate electrodes are provided that cross over the cell active regions. Memory cell patterns are provided between the cell gate electrodes and the cell active regions and extend toward the device isolation patterns. A tunnel insulation film is provided between the memory cell pattern and the cell active region. Related methods of fabricating nonvolatile memory devices are also provided herein.

    摘要翻译： 提供包括半导体衬底上的器件隔离图案的非易失性存储器件。 器件隔离图案限定半导体衬底的单元有源区和外围有源区。 提供跨越电池有源区的电池栅电极。 在单元栅极电极和单元有源区之间提供存储单元图案，并朝向器件隔离图案延伸。 在存储单元图形和单元有源区之间设置隧道绝缘膜。 本文还提供了制造非易失性存储器件的相关方法。

    Methods of forming nonvolatile memory devices
    7.
    发明授权
    Methods of forming nonvolatile memory devices 有权
    形成非易失性存储器件的方法

    公开(公告)号：US07399672B2

    公开(公告)日：2008-07-15

    申请号：US11375983

    申请日：2006-03-15

    申请人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Yoo-Cheol Shin ,  Jong-Sun Sel

    发明人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Yoo-Cheol Shin ,  Jong-Sun Sel

    IPC分类号： H01L21/336

    CPC分类号： H01L27/105 ,  B82Y10/00 ,  H01L21/823462 ,  H01L27/0629 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11568

    摘要： Methods of forming a memory device include forming a device isolation layer in a semiconductor substrate including a cell array region and a resistor region, the device isolation layer extending into the resistor region and defining an active region in the semiconductor substrate. A first conductive layer is formed on the device isolation layer in the resistor region. The semiconductor substrate is exposed in the cell array region. A cell insulation layer is formed on a portion of the semiconductor substrate including the exposed cell array region, the active region and the device isolation layer in the resistor region. A second conductive layer is formed on the cell insulation layer in the portion of the semiconductor substrate including the exposed cell array region, the active region and the device isolation layer in the resistor region. The second conductive layer is etched to form a cell gate electrode in the cell array region and to concurrently remove the second conductive layer from the resistor region and the first conductive layer is etched in the resistor region to form a resistor.

    摘要翻译： 形成存储器件的方法包括在包括单元阵列区域和电阻器区域的半导体衬底中形成器件隔离层，器件隔离层延伸到电阻器区域中并在半导体衬底中限定有源区域。 在电阻器区域中的器件隔离层上形成第一导电层。 半导体衬底暴露在电池阵列区域中。 在半导体衬底的包括电阻器区域中的暴露的电池阵列区域，有源区域和器件隔离层的部分上形成电池绝缘层。 在半导体衬底的包括电阻器区域中的暴露的电池阵列区域，有源区域和器件隔离层的部分中的单元绝缘层上形成第二导电层。 蚀刻第二导电层以在电池阵列区域中形成电池栅电极，并且同时从电阻器区域去除第二导电层，并且在电阻器区域中蚀刻第一导电层以形成电阻器。

    Nonvolatile memory devices and methods of forming the same
    9.
    发明申请
    Nonvolatile memory devices and methods of forming the same 有权
    非易失存储器件及其形成方法

    公开(公告)号：US20060208338A1

    公开(公告)日：2006-09-21

    申请号：US11375983

    申请日：2006-03-15

    申请人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Yoo-Cheol Shin ,  Jong-Sun Sel

    发明人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Yoo-Cheol Shin ,  Jong-Sun Sel

    IPC分类号： H01L29/00

    CPC分类号： H01L27/105 ,  B82Y10/00 ,  H01L21/823462 ,  H01L27/0629 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11568

    摘要： Methods of forming a memory device include forming a device isolation layer in a semiconductor substrate including a cell array region and a resistor region, the device isolation layer extending into the resistor region and defining an active region in the semiconductor substrate. A first conductive layer is formed on the device isolation layer in the resistor region. The semiconductor substrate is exposed in the cell array region. A cell insulation layer is formed on a portion of the semiconductor substrate including the exposed cell array region, the active region and the device isolation layer in the resistor region. A second conductive layer is formed on the cell insulation layer in the portion of the semiconductor substrate including the exposed cell array region, the active region and the device isolation layer in the resistor region. The second conductive layer is etched to form a cell gate electrode in the cell array region and to concurrently remove the second conductive layer from the resistor region and the first conductive layer is etched in the resistor region to form a resistor.

    摘要翻译： 形成存储器件的方法包括在包括单元阵列区域和电阻器区域的半导体衬底中形成器件隔离层，器件隔离层延伸到电阻器区域中并在半导体衬底中限定有源区域。 在电阻器区域中的器件隔离层上形成第一导电层。 半导体衬底暴露在电池阵列区域中。 在半导体衬底的包括电阻器区域中的暴露的电池阵列区域，有源区域和器件隔离层的部分上形成电池绝缘层。 在半导体衬底的包括电阻器区域中的暴露的电池阵列区域，有源区域和器件隔离层的部分中的单元绝缘层上形成第二导电层。 蚀刻第二导电层以在电池阵列区域中形成电池栅电极，并且同时从电阻器区域去除第二导电层，并且在电阻器区域中蚀刻第一导电层以形成电阻器。

    Nonvolatile memory device and fabricating method thereof
    10.
    发明授权
    Nonvolatile memory device and fabricating method thereof 有权
    非易失存储器件及其制造方法

    公开(公告)号：US09112045B2

    公开(公告)日：2015-08-18

    申请号：US13775833

    申请日：2013-02-25

    申请人： Ju-Hyung Kim ,  Chang-Seok Kang ,  Woon-Kyung Lee

    发明人： Ju-Hyung Kim ,  Chang-Seok Kang ,  Woon-Kyung Lee

    IPC分类号： H01L29/792 ,  H01L29/66 ,  H01L29/423 ,  H01L29/51 ,  H01L27/115

    CPC分类号： H01L29/792 ,  H01L27/11582 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/66833 ,  H01L29/7926

    摘要： A nonvolatile memory device comprises a channel pattern, a first interlayer dielectric film and a second interlayer dielectric film spaced apart from each other and stacked over each other, a gate pattern disposed between the first interlayer dielectric film and the second interlayer dielectric film, a trap layer disposed between the gate pattern and the channel pattern and a charge spreading inhibition layer disposed between the channel pattern and the first interlayer dielectric film and between the channel pattern and the second interlayer dielectric film. The charge spreading inhibition layer may include charges inside or on its surface. The charge spreading inhibition layer includes at least one of a metal oxide film or a metal nitride film or a metal oxynitride film having a greater dielectric constant than a silicon oxide film.

    摘要翻译： 非易失性存储器件包括彼此间隔开并且彼此堆叠的沟道图案，第一层间电介质膜和第二层间电介质膜，布置在第一层间电介质膜和第二层间电介质膜之间的栅极图案，阱 设置在栅极图案和沟道图案之间的层，以及设置在沟道图案和第一层间电介质膜之间以及沟道图案和第二层间电介质膜之间的电荷扩展抑制层。 电荷扩散抑制层可以包括其表面内部或其表面上的电荷。 电荷扩散抑制层包括金属氧化物膜或金属氮化物膜或具有比氧化硅膜更大的介电常数的金属氧氮化物膜中的至少一种。