公开(公告)号：US07571417B2

公开(公告)日：2009-08-04

申请号：US11012494

申请日：2004-12-16

申请人： Kyoko Izuha ,  Shigeki Nojima ,  Toshiya Kotani ,  Satoshi Tanaka

发明人： Kyoko Izuha ,  Shigeki Nojima ,  Toshiya Kotani ,  Satoshi Tanaka

IPC分类号： G06F17/50

CPC分类号： G03F7/70441 ,  G03F1/36

摘要： A pattern verification method includes preparing a desired pattern and a mask pattern forming the desired pattern on a substrate, defining at least one evaluation point on an edge of the desired pattern, defining at least one process parameter to compute the transferred/formed pattern, defining a reference value and a variable range for each of the process parameters, and computing a positional displacement for each first points corresponding to the evaluation point, first points computed using correction mask pattern and a plurality of combinations of parameter values obtained by varying the process parameters within the variable range or within the respective variable ranges. The positional displacement is a displacement between first point and the evaluation point. The method further includes computing a statistics of the positional displacements for each of the evaluation points, and outputting information modifying the mask pattern according to the statistics.

摘要翻译： 模式验证方法包括在衬底上制备期望图案和形成期望图案的掩模图案，在期望图案的边缘上限定至少一个评估点，限定至少一个过程参数以计算所转移/形成的图案，定义 针对每个处理参数的参考值和可变范围，并且计算与评估点相对应的每个第一点的位置偏移，使用校正掩模图案计算的第一点和通过改变处理参数获得的参数值的多个组合 在可变范围内或在相应的可变范围内。 位置偏移是第一点与评价点之间的位移。 该方法还包括计算每个评估点的位置偏移的统计量，并根据统计信息输出修改掩模图案的信息。

公开(公告)号：US20090192643A1

公开(公告)日：2009-07-30

申请号：US12354574

申请日：2009-01-15

申请人： Ayako Endo ,  Kenji Yoshida ,  Toshiya Kotani ,  Satoshi Tanaka

发明人： Ayako Endo ,  Kenji Yoshida ,  Toshiya Kotani ,  Satoshi Tanaka

IPC分类号： G06F19/00

CPC分类号： G05B19/41865 ,  G05B19/41885 ,  H01L22/20 ,  H01L2924/0002 ,  Y02P90/20 ,  Y02P90/26 ,  H01L2924/00

摘要： A process control method comprises adjusting a process condition in consideration of a performance variation among a plurality of manufacturing apparatuses, the performance variation affecting a finished shape of a pattern used to manufacture a semiconductor device, running a simulation of the finished shape under the adjusted process condition, extracting a dangerous point of the pattern affecting satisfaction from the result of the simulation, comparing a first process capability serving as a judgment standard to find whether a production schedule of the device is achieved with a second capability serving to form a dangerous pattern containing the dangerous point, and improving the second process when the second process capability is lower than the first process capability.

摘要翻译： 一种过程控制方法包括考虑多个制造装置之间的性能变化来调整工艺条件，影响用于制造半导体器件的图案的成品形状的性能变化，在调整过程下运行成品形状的模拟 从模拟结果中提取影响满意度的模式的危险点，比较作为判断标准的第一处理能力，以确定是否实现具有第二能力的设备的生产计划，以形成含有 危险点，并且当第二处理能力低于第一处理能力时，改进第二过程。

公开(公告)号：US07506301B2

公开(公告)日：2009-03-17

申请号：US11205180

申请日：2005-08-17

申请人： Toshiya Kotani ,  Satoshi Tanaka ,  Soichi Inoue

发明人： Toshiya Kotani ,  Satoshi Tanaka ,  Soichi Inoue

IPC分类号： G06F17/50

CPC分类号： G03F7/70441 ,  G03F1/36

摘要： A computer implemented method for correcting a mask pattern includes: predicting a displacement of a device pattern by using a mask pattern to form the device pattern and a variation of a process condition; determinating an optical proximity correction value so that the displacement falls within a displacement tolerance of the device pattern; and correcting the mask pattern using the optical proximity correction value.

公开(公告)号：US20080235650A1

公开(公告)日：2008-09-25

申请号：US12050764

申请日：2008-03-18

申请人： Takeshi Ito ,  Satoshi Tanaka ,  Toshiya Kotani ,  Tadahito Fujisawa ,  Koji Hashimoto

发明人： Takeshi Ito ,  Satoshi Tanaka ,  Toshiya Kotani ,  Tadahito Fujisawa ,  Koji Hashimoto

IPC分类号： G06F17/50

CPC分类号： G03F1/00

摘要： A pattern creation method, including laying out data of a most extreme end pattern of integrated circuit patterns on a first layer and laying out data of the integrated circuit patterns excluding the most extreme end pattern on a second layer, extracting data of a first most proximate pattern being most proximate to the most extreme end pattern from the second layer and converting the extracted data to a third layer, generating data of a contacting pattern which contacts both the first most proximate pattern and the most extreme end pattern in a fourth layer, generating data of a non-overlapping pattern of the contacting pattern excluding overlapping portions with the most extreme end pattern and the first most proximate pattern in a fifth layer, extracting data of a second most proximate pattern being most proximate to the non-overlapping pattern and converting the extracted data to the first layer.

摘要翻译： 一种图案创建方法，包括在第一层上布置集成电路图案的最极端格式的数据，并且在第二层上布置不包括最末端图案的集成电路图案的数据，提取第一最接近的数据 图案最接近于来自第二层的最末端图案，并将所提取的数据转换为第三层，产生在第四层中接触第一最近图案和最末端图案的接触图案的数据，产生 接触图案的非重叠图案的数据，不包括在第五层中具有最末端图案和最前端图案和第一最近图案的重叠部分，提取最接近图案的第二最接近图案的数据，其最接近非重叠图案并且转换 提取的数据到第一层。

公开(公告)号：US20070226676A1

公开(公告)日：2007-09-27

申请号：US11727288

申请日：2007-03-26

申请人： Kyoko Izuha ,  Toshiya Kotani ,  Satoshi Tanaka

发明人： Kyoko Izuha ,  Toshiya Kotani ,  Satoshi Tanaka

IPC分类号： G06F17/50

CPC分类号： G03F7/705

摘要： A method in which a desired pattern is compared with a finish pattern to be formed on a wafer, which is predicted from a design pattern, based on a calculation of a light beam intensity, and a deviation quantity of the finish pattern from the desired pattern at each edge of the finish pattern and the desired pattern is calculated, comprising setting a reference light beam intensity for setting the desired pattern on a wafer, setting an evaluation point for comparison of the finish pattern with the desired pattern, calculating a light beam intensity at the evaluation point, calculating a differentiation value of the light beam intensity at the evaluation point, calculating an intersection of the differentiation value with the reference light beam intensity, and calculating a difference between the intersection and the evaluation point, the difference defining an edge deviation quantity of the finish pattern from the desired pattern.

公开(公告)号：US20060033049A1

公开(公告)日：2006-02-16

申请号：US11200176

申请日：2005-08-10

申请人： Toshiya Kotani ,  Satoshi Tanaka ,  Shigeki Nojima ,  Soichi Inoue

发明人： Toshiya Kotani ,  Satoshi Tanaka ,  Shigeki Nojima ,  Soichi Inoue

IPC分类号： G21K5/10

CPC分类号： H01J37/3026 ,  G03F1/36 ,  G03F1/68

摘要： A design pattern data preparing method including preparing first mask pattern data based on first design pattern data, predicting a wafer pattern to be formed on a wafer corresponding to the first mask pattern based on the first mask pattern data, judging whether or not a finite difference between the predicted wafer pattern and the pattern to be formed on the wafer is within a predetermined allowable variation amount, correcting a portion of the first design pattern data selectively, the portion including a part corresponding to the finite difference when the finite difference is not within the allowable variation amount, and preparing second design pattern data by synthesizing the first mask pattern data corresponding to the portion including the part selectively corrected and data obtained by eliminating the first mask pattern data corresponding to the portion including the part selectively corrected from the first mask pattern data.

公开(公告)号：US20050177811A1

公开(公告)日：2005-08-11

申请号：US11105431

申请日：2005-04-14

申请人： Toshiya Kotani ,  Satoshi Tanaka ,  Koji Hashimoto ,  Soichi Inoue ,  Ichiro Mori

发明人： Toshiya Kotani ,  Satoshi Tanaka ,  Koji Hashimoto ,  Soichi Inoue ,  Ichiro Mori

IPC分类号： H01L21/66 ,  G06F17/50 ,  B05C11/00 ,  G01R31/26 ,  G03C5/00 ,  G03C8/00 ,  G03F9/00 ,  G06F9/45

CPC分类号： H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed is a method of setting a process parameter for use in manufacturing a semiconductor integrated circuit, comprising correcting a first pattern by using process parameter information to obtain a second pattern, the first pattern being one which corresponds to a design layout of the semiconductor integrated circuit, predicting a third pattern by using the process parameter information, the third pattern being one which corresponds to the second pattern and which is to be formed on a semiconductor wafer in an etching process, obtaining an evaluation value by comparing the third pattern with the first pattern, determining whether the evaluation value satisfies a preset condition, and changing the process parameter information when the evaluation value is found not to satisfy the preset condition.

摘要翻译： 公开了一种设置用于制造半导体集成电路的工艺参数的方法，包括通过使用工艺参数信息来校正第一图案以获得第二图案，第一图案是对应于半导体集成电路的设计布局的图案 ，通过使用处理参数信息来预测第三图案，在蚀刻工艺中，第三图案是对应于第二图案并且将形成在半导体晶片上的图案，通过将第三图案与第一图案进行比较来获得评估值 判定评估值是否满足预设条件，以及当评估值不满足预设条件时，改变处理参数信息。

公开(公告)号：US20120127454A1

公开(公告)日：2012-05-24

申请号：US13239449

申请日：2011-09-22

申请人： Hiroko NAKAMURA ,  Koji Asakawa ,  Shigeki Hattori ,  Satoshi Tanaka ,  Toshiya Kotani

发明人： Hiroko NAKAMURA ,  Koji Asakawa ,  Shigeki Hattori ,  Satoshi Tanaka ,  Toshiya Kotani

IPC分类号： G03B27/32

CPC分类号： G03F7/0002 ,  B81C1/00031 ,  B81C2201/0149 ,  B82Y10/00 ,  B82Y40/00

摘要： According to one embodiment, a pattern including first and second block phases is formed by self-assembling a block copolymer onto a film to be processed. The entire block copolymer present in a first region is removed under a first condition by carrying out energy beam irradiation and development, thereby leaving a pattern including the first and second block phases in a region other than the first region. The first block phase present in a second region is selectively removed under a second condition by carrying out energy beam irradiation and development, thereby leaving a pattern including the first and second block phases in an overlap region between a region other than the first region and a region other than the second region, and leaving a pattern of second block phase in the second region excluding the overlap region. The film is etched with the left patterns as masks.

摘要翻译： 根据一个实施方案，通过将嵌段共聚物自组装成待加工的膜来形成包括第一和第二嵌段相的图案。 存在于第一区域中的整个嵌段共聚物在第一条件下通过进行能量束照射和显影而除去，从而在第一区域以外的区域留下包括第一和第二嵌段相的图案。 存在于第二区域中的第一块相位通过进行能量束照射和显影而在第二条件下被选择性地去除，从而在包括第一区域和第一区域之间的重叠区域中留下包括第一和第二块相的图案， 区域，并且在除了重叠区域之外的第二区域中留下第二块相位的图案。 用左图案蚀刻该胶片作为掩模。

公开(公告)号：US08171433B2

公开(公告)日：2012-05-01

申请号：US12554495

申请日：2009-09-04

申请人： Masanori Takahashi ,  Toshiya Kotani ,  Satoshi Tanaka

发明人： Masanori Takahashi ,  Toshiya Kotani ,  Satoshi Tanaka

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： Method of calculating pattern-failure-occurrence-region comprising calculating a pattern failure occurrence region using relation information and a layout used for forming a convex section, the relation information being a relation between a distance from a formed pattern in a film to cover the convex section on a substrate to the convex section and a region in the film in which a shape of the formed pattern cannot satisfy a predetermined condition because of influence of the convex section.

摘要翻译： 计算图案故障发生区域的方法包括使用关系信息和用于形成凸部的布局来计算图案故障发生区域，所述关系信息是从胶片中形成的图案到覆盖凸起的距离之间的关系 由于凸部的影响，形成图案的形状不能满足规定条件的膜中的与凸部的基板上的区域。

公开(公告)号：US07934175B2

公开(公告)日：2011-04-26

申请号：US12062859

申请日：2008-04-04

申请人： Toshiya Kotani ,  Yasunobu Kai ,  Soichi Inoue ,  Satoshi Tanaka ,  Shigeki Nojima ,  Kazuyuki Masukawa ,  Koji Hashimoto

发明人： Toshiya Kotani ,  Yasunobu Kai ,  Soichi Inoue ,  Satoshi Tanaka ,  Shigeki Nojima ,  Kazuyuki Masukawa ,  Koji Hashimoto

IPC分类号： G06F17/50

CPC分类号： G03F7/70625 ,  G03F7/70525 ,  H01L22/12 ,  H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： A parameter adjustment method for a plurality of manufacturing devices to form a pattern of a semiconductor device on a substrate using the manufacturing devices includes: adjusting a parameter adjustable for a manufacturing device serving as a reference manufacturing device; obtaining a first shape of a pattern of a semiconductor device to be formed on a substrate; defining an adjustable parameter of another to-be-adjusted manufacturing; obtaining a second shape of the pattern formed on the substrate; calculating a difference amount between a reference finished shape and a to-be-adjusted finished shape; repeatedly calculating the difference amount by changing the to-be-adjusted parameter until the difference amount becomes equal to or less than a predetermined reference value; and outputting as a parameter of the to-be-adjusted manufacturing device the to-be-adjusted parameter.

摘要翻译： 用于使用该制造装置在基板上形成半导体器件的图案的多个制造装置的参数调整方法包括：调整可用于作为参考制造装置的制造装置的参数; 获得要在基板上形成的半导体器件的图案的第一形状; 定义另一个待调整制造的可调参数; 获得形成在所述基板上的所述图案的第二形状; 计算参考完成形状和待调整完成形状之间的差值; 通过改变待调整参数重复计算差值，直到差值变得等于或小于预定参考值; 并作为待调整制造装置的参数输出待调整参数。