公开(公告)号：US20090157252A1

公开(公告)日：2009-06-18

申请号：US12335984

申请日：2008-12-16

申请人： Makoto Saen ,  Kenichi Osada ,  Shigeru Oho

发明人： Makoto Saen ,  Kenichi Osada ,  Shigeru Oho

IPC分类号： G06F7/00

CPC分类号： G07C5/0816

摘要： In a vehicle electronic system including a plurality of LSI boards, LSIS which cannot control a user interface such as image or audio directly issue a command for notifying a vehicle occupant of its own information via networks and an information control LSI receives the request to output a message. A mechanism for setting priority of processings regarding LSI status information notification to be lower than that of an apparatus control processing is provided in each of LSIs and networks so that real-time property of the apparatus control processing is maintained. In order to reduce network load regarding the LSI status information notification, a message content itself is stored in a memory in a vehicle information processing unit previously so that only an ID for identifying the message content is transmitted.

摘要翻译： 在包括多个LSI板的车载电子系统中，无法控制诸如图像或音频的用户界面的LSIS直接发出用于通过网络通知车辆乘客自己的信息的命令，并且信息控制LSI接收输出 信息。 在LSI和网络的每一个中设置有用于将关于LSI状态信息通知的处理的优先级设置为低于设备控制处理的优先级的机制，从而保持设备控制处理的实时性。 为了减少关于LSI状态信息通知的网络负载，消息内容本身预先存储在车辆信息处理单元中的存储器中，从而仅发送用于识别消息内容的ID。

公开(公告)号：US07337251B2

公开(公告)日：2008-02-26

申请号：US11304567

申请日：2005-12-16

申请人： Makoto Saen ,  Hiroshi Ueda ,  Eiji Yamamoto

发明人： Makoto Saen ,  Hiroshi Ueda ,  Eiji Yamamoto

IPC分类号： G06F13/18

CPC分类号： G06F13/1605 ,  G06F13/362

摘要： The information processing device comprises first and second master circuits and an arbiter for arbitrating access rights to a bus to which the master circuits are connected. The arbiter has storage units retaining information representing priorities of the access rights, and an arbitration control logical unit for arbitrating the access rights of the master circuits based on the information. When the priority of the first master circuit is higher than the priority of the second master circuit and there is no access request from the first master circuit but there is an access request from the second master circuit, the arbitration control logical unit permits access of the second master circuit, and the storage units lower the priority of the second master circuit without changing the priority of the first master circuit.

摘要翻译： 信息处理设备包括第一和第二主电路以及用于仲裁与主电路连接的总线的访问权限的仲裁器。 仲裁器具有保存表示访问权限优先级的信息的存储单元，以及用于基于该信息来仲裁主电路的访问权限的仲裁控制逻辑单元。 当第一主电路的优先级高于第二主电路的优先级，并且没有来自第一主电路的访问请求，但是存在来自第二主电路的访问请求时，仲裁控制逻辑单元允许访问 第二主电路，并且存储单元降低第二主电路的优先级，而不改变第一主电路的优先级。

公开(公告)号：US20080022140A1

公开(公告)日：2008-01-24

申请号：US11826640

申请日：2007-07-17

申请人： Tetsuya Yamada ,  Makoto Saen ,  Satoshi Misaka ,  Keisuke Toyama ,  Kenichi Osada

发明人： Tetsuya Yamada ,  Makoto Saen ,  Satoshi Misaka ,  Keisuke Toyama ,  Kenichi Osada

IPC分类号： G06F1/26

CPC分类号： G06F1/206 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/16

摘要： A chip (1) includes: a resource manager (2); various kinds of functional blocks (3-6); a thermal sensor (13); and a performance counter (15). The resource manager manages tasks that the functional blocks execute, and determines a task progress (38) for each task from an activated ratio (α) provided from the performance counter and a deadline (39) contained in task information (33) and decides priority of each task. When the temperature detected by the thermal sensor during execution of a task is not less than a threshold (T_max), the resource manager reads out a power consumption budget (P_max) from a memory (9) which has been set to make the temperature below the threshold, and stops the clock fed to the functional block executing a task having a lower priority or lowers the frequency of the clock until a chip power consumption value (p_sum) becomes smaller than the power consumption budget.

摘要翻译： 芯片（1）包括：资源管理器（2）; 各种功能块（3〜6）; 热传感器（13）; 和性能计数器（15）。 所述资源管理器管理所述功能块执行的任务，并根据从所述性能计数器提供的激活的比率（α）和所述任务信息（33）中包含的最后期限（39）来确定每个任务的任务进度（38），并决定优先级 的每个任务。 当在执行任务期间由热传感器检测到的温度不小于阈值（T_max）时，资源管理器从设置为使温度低于的温度的存储器（9）读出功耗预算（P_max） 阈值，并且停止馈送到执行具有较低优先级的任务的功能块的时钟，或者降低时钟的频率，直到芯片功耗值（p_sum）变得小于功耗预算。

公开(公告)号：US20070260791A1

公开(公告)日：2007-11-08

申请号：US11822966

申请日：2007-07-11

申请人： Makoto Saen ,  Kei Suzuki

发明人： Makoto Saen ,  Kei Suzuki

IPC分类号： G06F13/20

CPC分类号： G06F13/364

摘要： A data processing device which, even if congestion occurs on a bus circuit of a specific processing circuit in an LSI in which multiple circuit modules are connected by buses, can fully actualize the performance potential of the system on chip. Buses and slave circuits on which accesses concentrate are provided with observation blocks. Each observation block has a mechanism to notify system control circuits such as a clock controller and master circuits such as CPU cores of the acquired status information, and each master circuit further has a mechanism capable of dynamically altering the priority order for notifying the bus circuits and slave circuits of the priority order of processing.

摘要翻译： 一种数据处理装置，即使在通过总线连接多个电路模块的LSI中的特定处理电路的总线电路上发生拥塞，也能够充分实现片上系统的性能潜力。 带有观察块的访问集中的巴士和从属电路。 每个观测块具有通知诸如时钟控制器和所获取的状态信息的CPU核心的主电路的系统控制电路的机制，并且每个主电路还具有能够动态地改变用于通知总线电路的优先级顺序的机构， 从电路处理的优先级顺序。