公开(公告)号：US20070229320A1

公开(公告)日：2007-10-04

申请号：US11693264

申请日：2007-03-29

申请人： Seung-Jun Bae ,  Seong-Jin Jang

发明人： Seung-Jun Bae ,  Seong-Jin Jang

IPC分类号： H03M7/00

CPC分类号： H03M5/145

摘要： DC balance encoded data is transmitted by transmitting a preamble of dummy data that is configured to provide an intermediate number of bits of a given logic value that is at least one bit of the given logic value but less than a maximum number of bits of the given logic value in the DC balance encoded data, to thereby reduce the simultaneous switching noise that is caused by transmission of a first word of DC balance encoded data. The preamble may contain one or more words of fixed and/or variable dummy data.

摘要翻译： 通过发送伪数据的前导码来发送DC平衡编码数据，该伪数据的前导码被配置为提供给定逻辑值的中间位数，该给定逻辑值是给定逻辑值的至少一位，但小于给定逻辑值的最大位数 DC平衡编码数据中的逻辑值，从而减少由DC平衡编码数据的第一字的传输引起的同时开关噪声。 前导码可以包含固定和/或可变虚拟数据的一个或多个单词。

公开(公告)号：US07237073B2

公开(公告)日：2007-06-26

申请号：US10737861

申请日：2003-12-18

申请人： Seong-Jin Jang

发明人： Seong-Jin Jang

IPC分类号： G06F5/00 ,  G06F13/00 ,  G11C7/10

CPC分类号： G11C7/1006 ,  G11C7/1051 ,  G11C7/1063 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/1096

摘要： A memory system and a method of reading and writing data to a memory device provide byte-by-byte write data insertion without adding extra pins or balls to the packaged device. Accordingly, the high frequency performance of the device can be improved.

摘要翻译： 存储器系统和将数据读取和写入存储器件的方法提供逐字节写入数据插入，而不会向封装器件添加额外的引脚或球。 因此，可以提高装置的高频性能。

公开(公告)号：US07092299B2

公开(公告)日：2006-08-15

申请号：US10792623

申请日：2004-03-03

申请人： Jin-Seok Kwak ,  Seong-Jin Jang ,  Young-Hyun Jun

发明人： Jin-Seok Kwak ,  Seong-Jin Jang ,  Young-Hyun Jun

IPC分类号： G11C7/00

CPC分类号： G11C5/063 ,  G11C7/10 ,  G11C7/1048

摘要： A memory system includes first and second memory devices having commonly connected data terminals and commonly connected memory control signal terminals, e.g., devices in respective first and second independently selectable memory banks that share common data lines and common memory control signal lines, such as column address strobe, row address strobe, write enable, and address signal lines. The first and second memory devices includes respective selective on-die termination (ODT) circuits configured to selectively provide first and second termination impedances at their respective data terminals responsive to a memory control signal at the commonly connected memory control signal terminals. The selective ODT circuits may produce the first termination impedance responsive to a memory write operation, and may produce the second termination impedance responsive to a memory read operation and/or expiration of a predetermined time interval following termination of the memory write operation. Preferably, the first termination impedance is less than the second termination impedance, and the selective ODT circuits provide the first termination impedance responsive to the memory write operation irrespective of which of the first and second memory devices is being written to.

摘要翻译： 存储器系统包括具有共同连接的数据端子和共同连接的存储器控​​制信号端子的第一和第二存储器件，例如共享公共数据线和公共存储器控制信号线的各自的第一和第二可独立选择的存储体中的器件，诸如列地址 选通，行地址选通，写使能和地址信号线。 第一和第二存储器件包括相应的选择性管芯端接（ODT）电路，其被配置为响应于在共同连接的存储器控​​制信号端子处的存储器控​​制信号在它们各自的数据端口选择性地提供第一和第二终端阻抗。 响应于存储器写入操作，选择性ODT电路可以产生第一终止阻抗，并且可以在存储器写入操作终止之后响应于存储器读取操作和/或预定时间间隔的期满而产生第二终止阻抗。 优选地，第一终端阻抗小于第二终端阻抗，并且选择性ODT电路响应于存储器写入操作提供第一终止阻抗，而与正在写入的第一和第二存储器件中的哪一个无关。

公开(公告)号：US20060060986A1

公开(公告)日：2006-03-23

申请号：US11229257

申请日：2005-09-16

申请人： Sung-Hoon Kim ,  Young-Chul Cho ,  Kwang-Il Park ,  Seong-Jin Jang

发明人： Sung-Hoon Kim ,  Young-Chul Cho ,  Kwang-Il Park ,  Seong-Jin Jang

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor memory device and a power line arrangement method are disclosed. The semiconductor memory device includes a plurality of pads, each pad including an upper pad and a lower pad arranged below the upper pad, wherein pad power lines are arranged below the lower pads of the plurality of pads in a direction of crossing the pads to interconnect the pads that transmit the same level of electrical power among the plurality of pads.

公开(公告)号：US20060038577A1

公开(公告)日：2006-02-23

申请号：US11191376

申请日：2005-07-28

申请人： Seong-Jin Jang

发明人： Seong-Jin Jang

IPC分类号： G01R31/02

CPC分类号： G05F3/02 ,  G11C5/147

摘要： A circuit for generating a reference voltage includes a first reference voltage generating circuit disposed outside a chip and a second reference voltage generating circuit disposed inside the chip. The first and second reference voltage generating circuits output first and second reference voltages to first and second output terminals, respectively. The second reference voltage generating circuit includes at least one pull-up resistor and at least one pull-down resistor. The pull-up resistor is coupled between a first node where an internal power supply voltage is coupled and the second output terminal. The pull-down resistor is coupled between a second node and the second output terminal, wherein a voltage at the second node is relatively lower than a voltage at the first node. A third reference voltage is outputted from a node where the first output terminal is coupled to the second output terminal.

公开(公告)号：US20050068840A1

公开(公告)日：2005-03-31

申请号：US10943514

申请日：2004-09-17

申请人： Min-Sang Park ,  Yu-Lim Lee ,  Seong-Jin Jang

发明人： Min-Sang Park ,  Yu-Lim Lee ,  Seong-Jin Jang

IPC分类号： G11C11/407 ,  G11C8/02 ,  G11C8/08 ,  G11C11/401 ,  G11C11/4063

CPC分类号： G11C8/12

摘要： A method for activating a word line segment of a semiconductor memory selected based on a row address provided to the memory can include activating a first word line segment selected by a row address and a command type and avoiding activating a second word line segment selected by the row address. Related devices are also disclosed.

摘要翻译： 用于激活基于提供给存储器的行地址选择的半导体存储器的字线段的方法可以包括激活由行地址和命令类型选择的第一字线段，并且避免激活由第二字线段选择的第二字线段 行地址。 还公开了相关设备。

公开(公告)号：US06801067B2

公开(公告)日：2004-10-05

申请号：US10404102

申请日：2003-04-02

申请人： Seong-Jin Jang

发明人： Seong-Jin Jang

IPC分类号： H03H1126

CPC分类号： H03K5/135 ,  H03K5/13 ,  H03L7/08

摘要： A method of generating a clock may use an analog synchronous mirror delay (ASMD) circuit with a duty cycle correction scheme, and an internal clock generator may use one or more of the ASMD circuits, The ASMD circuit may include a comparator with first and second input terminals that generates an output clock based on a comparison result between a signal on the first input terminal and a signal on the second input terminal, a first precharge circuit connected to the first input terminal and precharging the first input terminal, and a second precharge circuit connected to the second input terminal and precharging the second input terminal. The ASMD circuit may also include a first pair of discharge circuits discharging the first input terminal within first and second cycles of the input clock, and a second pair of discharge circuits discharging the second input terminal within first and second cycles of the input clock.

摘要翻译： 产生时钟的方法可以使用具有占空比校正方案的模拟同步镜延迟（ASMD）电路，并且内部时钟发生器可以使用一个或多个ASMD电路.ASMD电路可以包括比较器，其具有第一和第二 输入端子，其基于第一输入端子上的信号与第二输入端子上的信号之间的比较结果产生输出时钟;第一预充电电路，连接到第一输入端子并对第一输入端子进行预充电;以及第二预充电 电路连接到第二输入端并对第二输入端子进行预充电。 ASMD电路还可以包括在输入时钟的第一和第二周期内对第一输入端子进行放电的第一对放电电路，以及在输入时钟的第一和第二周期内对第二输入端子进行放电的第二对放电电路。

公开(公告)号：US06750692B2

公开(公告)日：2004-06-15

申请号：US10413961

申请日：2003-04-15

申请人： Seong-Jin Jang

发明人： Seong-Jin Jang

IPC分类号： G06F104

CPC分类号： G06F1/04 ,  H03K3/03

摘要： The present invention discloses a circuit and a method for generating an internal clock signal, where the internal clock signal generation circuit includes a first delay portion for delaying an external clock signal by a first delay time, divides for dividing an output signal from the first delay portion, a first signal generator for generating a first signal with a pulse width equivalent to a skew monitor time by delaying an output signal from the divider by a second delay time and by combining the output signal from the divider with a signal delayed by the second delay time, a second signal generater for generating a second signal with a pulse width equivalent to a third delay time at a falling or rising edge of the output signal from the first delay portion, a time/digital signal converter for converting the skew monitor time equavalent to the pulse width of the first signal into first and second digital signals in response to the first signal, and a digital signal/time converter for reproducing the skew monitor time by inputting the first and the second digital signals in response to the second signal and generating the internal clock signal being delayed by a fourth delay time from the skew monitor time reproduced.

摘要翻译： 本发明公开了一种用于产生内部时钟信号的电路和方法，其中内部时钟信号产生电路包括用于将外部时钟信号延迟第一延迟时间的第一延迟部分，用于将来自第一延迟的输出信号分频 第一信号发生器，用于通过将来自分频器的输出信号延迟第二延迟时间并通过将来自分频器的输出信号与延迟第二延迟时间的信号组合，产生具有等于歪斜监视时间的脉冲宽度的第一信号 延迟时间，第二信号发生器，用于在来自第一延迟部分的输出信号的下降沿或上升沿产生具有等于第三延迟时间的脉冲宽度的第二信号;时间/数字信号转换器，用于将偏斜监视时间 响应于第一信号而将第一信号的脉冲宽度偏置为第一和第二数字信号，以及数字信号/时间转换器fo r通过响应于第二信号输入第一和第二数字信号并产生从再现的偏斜监视时间延迟第四延迟时间的内部时钟信号来再现偏斜监视时间。

公开(公告)号：US06653889B2

公开(公告)日：2003-11-25

申请号：US10188927

申请日：2002-07-02

申请人： Seong-Jin Jang ,  Young-Hyun Jun

发明人： Seong-Jin Jang ,  Young-Hyun Jun

IPC分类号： G05F110

CPC分类号： G11C5/145 ,  H02M3/073

摘要： Integrated circuit voltage generating circuits include an integrated circuit substrate, a first voltage generating circuit in the integrated substrate that is configured to generate a first voltage from a power supply voltage, and a second voltage generating circuit in the integrated circuit substrate that is configured to generate a second voltage that is different from the first voltage from the power supply voltage. A shared capacitor in the integrated circuit substrate is connected to both the first voltage generating circuit and to the second voltage generating circuit. The shared capacitor is used by the first voltage generating circuit and the second voltage generating circuit, to generate the first and second voltages.

摘要翻译： 集成电路电压产生电路包括集成电路基板，被配置为从电源电压产生第一电压的集成基板中的第一电压产生电路，以及集成电路基板中的第二电压产生电路，其被配置为产生 与电源电压的第一电压不同的第二电压。 集成电路基板中的共用电容器连接到第一电压产生电路和第二电压产生电路。 共享电容器由第一电压产生电路和第二电压产生电路用于产生第一和第二电压。

公开(公告)号：US6043697A

公开(公告)日：2000-03-28

申请号：US39337

申请日：1998-03-16

申请人： Seong-Jin Jang

发明人： Seong-Jin Jang

IPC分类号： H03K19/00 ,  G06F1/04 ,  G06F1/10 ,  G06F1/12 ,  G11C11/407 ,  G11C11/409 ,  H03K5/135 ,  G11C7/00

CPC分类号： G06F1/04

摘要： A clock signal control apparatus for a data output buffer that controls a data access time and an output signal maintaining time of the data output buffer based on a period of an input first clock signal. The apparatus includes a clock signal generator for generating a second clock signal having a period controlled by a period of a first clock signal, a clock signal controller and a data output buffer. The clock signal controller delays the second clock signal from the clock signal generator for a predetermined time, generates an output enable signal and a third clock signal in accordance with the second clock signal. A data output buffer receives a data signal, buffers the data signal in accordance with the third clock signal and the output enable signal from the clock signal controller, and generates an output data signal. The second clock signal has one of a plurality of periods based on the first clock signal.

摘要翻译： 一种用于数据输出缓冲器的时钟信号控制装置，其基于输入的第一时钟信号的周期来控制数据存取时间和保持数据输出缓冲器的时间的输出信号。 该装置包括时钟信号发生器，用于产生具有由第一时钟信号的周期控制的周期的第二时钟信号，时钟信号控制器和数据输出缓冲器。 时钟信号控制器将来自时钟信号发生器的第二时钟信号延迟预定时间，根据第二时钟信号产生输出使能信号和第三时钟信号。 数据输出缓冲器接收数据信号，根据来自时钟信号控制器的第三时钟信号和输出使能信号缓冲数据信号，并产生输出数据信号。 第二时钟信号基于第一时钟信号具有多个周期中的一个。