公开(公告)号：US07945830B2

公开(公告)日：2011-05-17

申请号：US12776075

申请日：2010-05-07

申请人： Laung-Terng (L.-T.) Wang ,  Xiaoqing Wen

发明人： Laung-Terng (L.-T.) Wang ,  Xiaoqing Wen

IPC分类号： G01R31/28

CPC分类号： G06F11/27 ,  G01R31/318586 ,  G01R31/318594

摘要： A method and apparatus for testing or diagnosing faults in a scan-based integrated circuit using a unified self-test and scan-test technique. The method and apparatus comprises using a unified test controller to ease prototype debug and production test. The unified test controller further comprises using a capture clock generator and a plurality of domain clock generators each embedded in a clock domain to perform self-test or scan-test. The capture clocks generated by the capture clock generator are used to guide at-speed or reduced-speed self-test (or scan-test) within each clock domain. The frequency of these capture clocks can be totally unrelated to those of system clocks controlling the clock domains. This unified approach allows designers to test or diagnose stuck-type and non-stuck-type faults with a low-cost DFT (design-for-test) tester or a low-cost DFT debugger. A computer-aided design (CAD) method is further developed to realize the method and synthesize the apparatus.

摘要翻译： 一种用于使用统一的自检和扫描测试技术来测试或诊断基于扫描的集成电路中的故障的方法和装置。 该方法和装置包括使用统一的测试控制器来简化原型调试和生产测试。 统一的测试控制器还包括使用捕获时钟发生器和每个嵌入在时钟域中的多个域时钟发生器来执行自检或扫描测试。 由捕获时钟发生器产生的捕获时钟用于引导每个时钟域内的速度或速度自检（或扫描测试）。 这些捕获时钟的频率与控制时钟域的系统时钟的频率完全无关。 这种统一的方法允许设计人员使用低成本DFT（设计测试）测试仪或低成本DFT调试器来测试或诊断卡住型和非卡住型故障。 进一步开发了计算机辅助设计（CAD）方法，实现了该方法并综合了该装置。

公开(公告)号：US07904773B2

公开(公告)日：2011-03-08

申请号：US12285269

申请日：2008-10-01

申请人： Laung-Terng (L. T.) Wang ,  Meng-Chyi Lin ,  Xiaoqing Wen ,  Hsin-Po Wang ,  Chi-Chan Hsu ,  Shih-Chia Kao ,  Fei-Sheng Hsu

发明人： Laung-Terng (L. T.) Wang ,  Meng-Chyi Lin ,  Xiaoqing Wen ,  Hsin-Po Wang ,  Chi-Chan Hsu ,  Shih-Chia Kao ,  Fei-Sheng Hsu

IPC分类号： G01R31/28

CPC分类号： G01R31/318594 ,  G01R31/31704 ,  G01R31/318552 ,  G01R31/31858

摘要： A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in a scan-based integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain has a plurality of scan cells. The method and apparatus will apply an ordered sequence of capture clocks to all scan cells within N clock domains where one or more capture clocks must contain one or more shift clock pulses during the capture operation. A computer-aided design (CAD) method is further developed to realize the method and synthesize the apparatus. In order to further improve the circuit's fault coverage, a CAD method and apparatus are further developed to minimize the memory usage and generate scan patterns for full-scan and feed-forward partial-scan designs containing transparent storage cells, asynchronous set/reset signals, tri-state busses, and low-power gated clocks.

摘要翻译： 一种用于提供有序捕获时钟以检测或定位N个时钟域内的故障的方法和装置，以及在自检或扫描测试模式中跨过基于扫描的集成电路或电路组件中的任何两个时钟域的故障，其中N≥1和 每个域具有多个扫描单元。 该方法和装置将对N个时钟域内的所有扫描单元应用有序序列的捕获时钟，其中一个或多个捕获时钟在捕获操作期间必须包含一个或多个移位时钟脉冲。 进一步开发了计算机辅助设计（CAD）方法，实现了该方法并综合了该装置。 为了进一步改善电路的故障覆盖范围，进一步开发了一种CAD方法和装置，以最小化存储器使用并产生包含透明存储单元，异步设置/复位信号的全扫描和前馈部分扫描设计的扫描模式， 三态总线和低功率门控时钟。

公开(公告)号：US20100218062A1

公开(公告)日：2010-08-26

申请号：US12776075

申请日：2010-05-07

申请人： Laung-Terng (L.-T.) WANG ,  Xiaoqing Wen

发明人： Laung-Terng (L.-T.) WANG ,  Xiaoqing Wen

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G06F11/27 ,  G01R31/318586 ,  G01R31/318594

摘要： A method and apparatus for testing or diagnosing faults in a scan-based integrated circuit using a unified self-test and scan-test technique. The method and apparatus comprises using a unified test controller to ease prototype debug and production test. The unified test controller further comprises using a capture clock generator and a plurality of domain clock generators each embedded in a clock domain to perform self-test or scan-test. The capture clocks generated by the capture clock generator are used to guide at-speed or reduced-speed self-test (or scan-test) within each clock domain. The frequency of these capture clocks can be totally unrelated to those of system clocks controlling the clock domains. This unified approach allows designers to test or diagnose stuck-type and non-stuck-type faults with a low-cost DFT (design-for-test) tester or a low-cost DFT debugger. A computer-aided design (CAD) method is further developed to realize the method and synthesize the apparatus.

摘要翻译： 一种用于使用统一的自检和扫描测试技术来测试或诊断基于扫描的集成电路中的故障的方法和装置。 该方法和装置包括使用统一的测试控制器来简化原型调试和生产测试。 统一的测试控制器还包括使用捕获时钟发生器和每个嵌入在时钟域中的多个域时钟发生器来执行自检或扫描测试。 由捕获时钟发生器产生的捕获时钟用于引导每个时钟域内的速度或速度自检（或扫描测试）。 这些捕获时钟的频率与控制时钟域的系统时钟的频率完全无关。 这种统一的方法允许设计人员使用低成本DFT（设计测试）测试仪或低成本DFT调试器来测试或诊断卡住型和非卡住型故障。 进一步开发了计算机辅助设计（CAD）方法，实现了该方法并综合了该装置。

公开(公告)号：US20100095179A1

公开(公告)日：2010-04-15

申请号：US12597106

申请日：2009-04-11

申请人： Xiaoqing Wen ,  Kohei Miyase ,  Seiji Kajihara

发明人： Xiaoqing Wen ,  Kohei Miyase ,  Seiji Kajihara

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G01R31/318307 ,  G01R31/31813 ,  G01R31/318371

摘要： A test pattern generation method for determining if a combinational portion 17 is defective, by applying test patterns to a semiconductor integrated circuit 10 and comparing responses to the test patterns with expected responses, the method including: a first step of generating test patterns having logic bits for detecting defects and unspecified bits; a second step of selecting critical paths 19, 19a, 19b generated by the application of the test patterns; a third step of identifying critical gates on the critical paths 19, 19a, 19b; and a fourth step of determining unspecified bits so that a critical capture transition metric, which indicates the number of the critical gates whose states are changed, is reduced; wherein by reducing the critical capture transition metric, output delays from the critical paths 19, 19a, 19b are prevented, and thereby false testing can be avoided.

摘要翻译： 一种测试图形生成方法，用于通过将测试图案应用于半导体集成电路10并且将测试图案的响应与期望的响应进行比较来确定组合部分17是否有缺陷，该方法包括：产生具有逻辑位的测试图案的第一步骤 用于检测缺陷和未指定位; 选择通过应用测试图形生成的关键路径19,19a，19b的第二步骤; 在关键路径19,19a，19b上识别关键闸门的第三步骤; 以及确定未指定位的第四步骤，使得指示其状态改变的关键门的数量的关键捕获转换度量被减小; 其中通过减小关键捕获转移度量，防止从关键路径19,19a，19b的输出延迟，从而可以避免错误测试。

公开(公告)号：US07032148B2

公开(公告)日：2006-04-18

申请号：US10876784

申请日：2004-06-28

申请人： Laung-Terng (L.-T.) Wang ,  Shun-Miin (Sam) Wang ,  Khader S. Abdel-Hafez ,  Xiaoqing Wen ,  Boryau (Jack) Sheu

发明人： Laung-Terng (L.-T.) Wang ,  Shun-Miin (Sam) Wang ,  Khader S. Abdel-Hafez ,  Xiaoqing Wen ,  Boryau (Jack) Sheu

IPC分类号： G01R31/3177 ,  G01R31/3181 ,  G01R31/3185

CPC分类号： G01R31/318547 ,  G01R31/318536

摘要： A method and apparatus for selectively masking off unknown (‘x’) captured scan data in first selected scan cells 220 from propagating through the scan chains 221 for test, debug, diagnosis, and yield improvement of a scan-based integrated circuit 207 in a selected scan-test mode 232 or selected self-test mode. The scan-based integrated circuit 207 contains a plurality of scan chains 221, a plurality of pattern generators 208, a plurality of pattern compactors 213, with each scan chain 221 comprising multiple scan cells 220, 222 coupled in series. The method and apparatus further includes an output-mask controller 211 and an output-mask network 212 embedded on the scan data input path of second selected scan cells 222, or a set/reset controller controlling selected set/reset inputs of second selected scan cells. A synthesis method is also proposed for synthesizing the output-mask controller 211 and the set/reset controller.

摘要翻译： 一种用于选择性地遮蔽第一选定扫描单元220中的未知（'x“）捕获的扫描数据的方法和装置，其传播通过扫描链221，用于测试，调试，诊断和屈服改善基于扫描的集成电路207 选择扫描测试模式232或选择自检模式。 基于扫描的集成电路207包含多个扫描链221，多个图案生成器208，多个图案压缩器213，每个扫描链221包括串联耦合的多个扫描单元220,222。 该方法和装置还包括输入掩模控制器211和嵌入在第二选择的扫描单元222的扫描数据输入路径上的输出屏蔽网络212，或者设置/复位控制器控制第二选择的扫描单元的选定的设置/复位输入 。 还提出了一种用于合成输出掩模控制器211和设置/复位控制器的合成方法。

公开(公告)号：US08589751B2

公开(公告)日：2013-11-19

申请号：US12761643

申请日：2010-04-16

申请人： Kohei Miyase ,  Xiaoqing Wen ,  Seiji Kajihara

发明人： Kohei Miyase ,  Xiaoqing Wen ,  Seiji Kajihara

IPC分类号： G01R31/28

CPC分类号： G01R31/318307 ,  G01R31/3183 ,  G01R31/318544 ,  G01R31/318594

摘要： The provided are a don't-care-bit identification method and program for identifying don't-care-bits from the first and the second input vectors in an input-vector pair while keeping the sensitization status of paths, in a combinational circuit, sensitized by applying the first and the second input vectors in serial to input lines of combinational circuit. The method identifies an unspecified bit from the first and the second input vectors V1 and V2 composed of logic values 0 and 1, which are applied to the combinational portion in a sequential circuit or to an independent combinational circuit. The method includes an identification step for identifying an unspecified bit from the first and the second input vectors, while keeping sensitization status of a part of or all of the paths, sensitized by applying the first and the second input vectors.

摘要翻译： 所提供的是一种不必要的位识别方法和程序，用于在保持路径的敏化状态的同时将输入矢量对中的第一和第二输入向量识别不必要位，并在组合电路中 通过将第一和第二输入向量串行地应用于组合电路的输入线而变得敏感。 该方法从由逻辑值0和1组成的第一和第二输入向量V1和V2中识别未指定的位，其被施加到顺序电路中的组合部分或独立组合电路。 该方法包括用于从第一和第二输入向量识别未指定比特的识别步骤，同时保持通过应用第一和第二输入向量敏感的一部分或全部路径的敏化状态。

公开(公告)号：US08429472B2

公开(公告)日：2013-04-23

申请号：US13059541

申请日：2009-07-30

申请人： Kohei Miyase ,  Xiaoqing Wen ,  Seiji Kajihara ,  Yuta Yamato

发明人： Kohei Miyase ,  Xiaoqing Wen ,  Seiji Kajihara ,  Yuta Yamato

IPC分类号： G01R31/28

CPC分类号： G01R31/318547

摘要： Provided are a generation device to reduce launch switching activity, yield loss risk, and power consumption of testing, even in the at-speed scan testing, even with a small number of don't-care (X) bits in input bits as in test compression, without any impact on test data volume, fault coverage, performance, and circuit design, by putting focus on internal lines in the circuit. The generation device includes a target internal line selection unit, a target internal line distinction unit, an identification unit that identifies a bit to be an unspecified bit and a bit to be a logic bit in the input bits, and an assignment unit that assigns a logic value 1 or a logic value 0 to unspecified bits in the input bits. The identification unit includes an unspecified bit identification unit and an input logic bit identification unit.

摘要翻译： 即使在高速扫描测试中，即使在输入位中使用少量不小心（X）位，也提供了降低发射切换活动，产量损失风险和测试功耗的发电设备，如 测试压缩，对测试数据量，故障覆盖率，性能和电路设计没有任何影响，重点放在电路中的内部线路上。 生成装置包括目标内线选择单元，目标内线区分单元，识别作为未指定位的位和识别输入位中的逻辑位的位的识别单元，以及分配单元， 逻辑值1或逻辑值0，以输入位中的未指定位。 识别单元包括未指定位识别单元和输入逻辑位识别单元。

公开(公告)号：US08117513B2

公开(公告)日：2012-02-14

申请号：US11887383

申请日：2006-03-27

申请人： Xiaoqing Wen ,  Seiji Kajihara

发明人： Xiaoqing Wen ,  Seiji Kajihara

IPC分类号： G01R31/28 ,  G06F11/00

CPC分类号： G01R31/318547 ,  G01R31/318502

摘要： In a combinational portion, when there is one or more unspecified bits in pseudo external input lines and there is no unspecified bit in pseudo external output lines, an assigning operation is carried out. In the combinational portion, when there is one or more unspecified bits in the pseudo external output lines and there is no unspecified bit in the pseudo external input lines, first and second justifying operations are carried out, and a necessary logic value is determined for an unspecified bit of the test cube. In the combinational portion, when there are one more unspecified bits not only in the pseudo external input lines but also the pseudo external output lines, an assigning operation, a justifying operation or first and second assigning/justifying operations are performed upon a focused bit pair.

摘要翻译： 在组合部分中，当在伪外部输入线中存在一个或多个未指定比特并且在伪外部输出线中没有未指定的比特时，执行分配操作。 在组合部分中，当在伪外部输出线路中存在一个或多个未指定比特并且在伪外部输入线路中没有未指定比特时，执行第一和第二对齐操作，并且确定必要的逻辑值 未指定位的测试立方体。 在组合部分中，当不仅在伪外部输入线路中还有伪外部输出线路还有一个未指定的位时，在聚焦位对上执行分配操作，对齐操作或第一和第二分配/调整操作 。

公开(公告)号：US07971118B2

公开(公告)日：2011-06-28

申请号：US12129746

申请日：2008-05-30

申请人： Xiaoqing Wen ,  Seiji Kajihara ,  Kohei Miyase ,  Yoshihiro Minamoto ,  Hiroshi Date

发明人： Xiaoqing Wen ,  Seiji Kajihara ,  Kohei Miyase ,  Yoshihiro Minamoto ,  Hiroshi Date

IPC分类号： G01R31/28 ,  G06F11/00

CPC分类号： G01R31/318547 ,  G01R31/318335 ,  G01R31/318502

摘要： Provided are a conversion device and others for converting a test vector set so as to reduce a logic value difference generated before and after scan capture in outputs of scan cells included in a full scan sequential circuit. A conversion device converts a test vector set corresponding to the full scan sequential circuit. The conversion device comprises a setting unit for setting a candidate bit which can be a don't care bit and a fixed bit which cannot be the don't care bit according to predetermined constraint conditions based on an input-output relationship in the logic circuit in order to identify the don't care bit identifiable as don't care from each test vector of the test vector set, and a logic value deciding unit for deciding a logic value for the don't care bit in view of a relationship in a plurality of bit pairs in relation to a test cube including the don't care bit identified by the setting unit.

摘要翻译： 提供了一种转换装置和其他用于转换测试矢量集，以便减少在全扫描时序电路中包括的扫描单元的输出中扫描捕获之前和之后产生的逻辑值差。 转换装置转换对应于全扫描时序电路的测试矢量集。 转换装置包括：设置单元，用于根据预定的约束条件，基于逻辑电路中的输入 - 输出关系设置可以是无关位的候选比特和不能不关心比特的固定比特 为了识别不关心的位，可以从测试向量集合的每个测试向量不关心，以及逻辑值决定单元，用于根据关系中的关系来确定无关位的逻辑值 相对于包括由设置单元标识的无关位的测试立方体的多个位对。

公开(公告)号：US20110140734A1

公开(公告)日：2011-06-16

申请号：US13059541

申请日：2009-07-30

申请人： Kohei Miyase ,  Xiaoqing Wen ,  Seiji Kajihara ,  Yuta Yamato

发明人： Kohei Miyase ,  Xiaoqing Wen ,  Seiji Kajihara ,  Yuta Yamato

IPC分类号： H03K19/00

CPC分类号： G01R31/318547

摘要： Provided are a generation device to reduce launch switching activity, yield loss risk, and power consumption of testing, even in the at-speed scan testing, even with a small number of don't-care (X) bits in input bits as in test compression, without any impact on test data volume, fault coverage, performance, and circuit design, by putting focus on internal lines in the circuit. The generation device includes a target internal line selection unit, a target internal line distinction unit, an identification unit that identifies a bit to be an unspecified bit and a bit to be a logic bit in the input bits, and an assignment unit that assigns a logic value 1 or a logic value 0 to unspecified bits in the input bits. The identification unit includes an unspecified bit identification unit and an input logic bit identification unit.

摘要翻译： 即使在高速扫描测试中，即使在输入位中使用少量不小心（X）位，也提供了降低发射切换活动，产量损失风险和测试功耗的发电设备，如 测试压缩，对测试数据量，故障覆盖率，性能和电路设计没有任何影响，重点放在电路中的内部线路上。 生成装置包括目标内线选择单元，目标内线区分单元，识别作为未指定位的位和识别输入位中的逻辑位的位的识别单元，以及分配单元， 逻辑值1或逻辑值0，以输入位中的未指定位。 识别单元包括未指定位识别单元和输入逻辑位识别单元。