中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

232 records (took 0.028 seconds)

    SELF-ALIGNED MEMORY DECKS IN CROSS-POINT MEMORY ARRAYS
    51.
    发明申请
    SELF-ALIGNED MEMORY DECKS IN CROSS-POINT MEMORY ARRAYS 审中-公开

    公开(公告)号：US20200075858A1

    公开(公告)日：2020-03-05

    申请号：US16665955

    申请日：2019-10-28

    Applicant: Micron Technology, Inc.

    Inventor： Agostino Pirovano ,  Fabio Pellizzer ,  Anna Maria Conti ,  Andrea Redaelli ,  Innocenzo Tortorelli

    IPC: H01L45/00 ,  H01L27/24

    Abstract: A multi-layer memory device with an array having multiple memory decks of self-selecting memory cells is provided in which N memory decks may be fabricated with N+1 mask operations. The multiple memory decks may be self-aligned and certain manufacturing operations may be performed for multiple memory decks at the same time. For example, patterning a bit line direction of a first memory deck and a word line direction in a second memory deck above the first memory deck may be performed in a single masking operation, and both decks may be etched in a same subsequent etching operation. Such techniques may provide efficient fabrication which may allow for enhanced throughput, additional capacity, and higher yield for fabrication facilities relative to processing techniques in which each memory deck is processed using two or more mask and etch operations per memory deck.

    Arrays Of Memory Cells And Methods Of Forming An Array Of Elevationally-Outer-Tier Memory Cells And Elevationally-Inner-Tier Memory Cells
    52.
    发明申请
    Arrays Of Memory Cells And Methods Of Forming An Array Of Elevationally-Outer-Tier Memory Cells And Elevationally-Inner-Tier Memory Cells 审中-公开

    公开(公告)号：US20200013829A1

    公开(公告)日：2020-01-09

    申请号：US16575743

    申请日：2019-09-19

    Applicant: Micron Technology, Inc.

    Inventor： Anna Maria Conti ,  Agostino Pirovano ,  Andrea Redaelli

    IPC: H01L27/24

    Abstract: A method of forming an array of memory cells, where the array comprises an elevationally-inner tier of memory cells comprising spaced-inner-tier-lower-first-conductive lines and inner-tier-programmable material directly there-above, an elevationally-outer tier of memory cells comprising spaced-outer-tier-lower-first-conductive lines and outer-tier-programmable material directly there-above, and spaced-upper-second-conductive lines that are electrically shared by the outer-tier memory cells and the inner-tier memory cells, comprises depositing conductor material for all of the shared-spaced-upper-second-conductive lines. All of the conductor material for all of the shared-spaced-upper-second-conductive lines is patterned using only a single masking step. Other method embodiments and arrays of memory cells independent of method of manufacture are disclosed.

    TECHNIQUES TO ACCESS A SELF-SELECTING MEMORY DEVICE
    53.
    发明申请
    TECHNIQUES TO ACCESS A SELF-SELECTING MEMORY DEVICE 审中-公开

    公开(公告)号：US20190362789A1

    公开(公告)日：2019-11-28

    申请号：US16419821

    申请日：2019-05-22

    Applicant: Micron Technology, Inc.

    Inventor： Innocenzo Tortorelli ,  Andrea Redaelli ,  Agostino Pirovano ,  Fabio Pellizzer ,  Mario Allegra ,  Paolo Fantini

    IPC: G11C13/00 ,  G11C11/56 ,  H01L27/24

    Abstract: Methods, systems, and devices related to techniques to access a self-selecting memory device are described. A self-selecting memory cell may store one or more bits of data represented by different threshold voltages of the self-selecting memory cell. A programming pulse may be varied to establish the different threshold voltages by modifying one or more time durations during which a fixed level of voltage or current is maintained across the self-selecting memory cell. The self-selecting memory cell may include a chalcogenide alloy. A non-uniform distribution of an element in the chalcogenide alloy may determine a particular threshold voltage of the self-selecting memory cell. The shape of the programming pulse may be configured to modify a distribution of the element in the chalcogenide alloy based on a desired logic state of the self-selecting memory cell.

    Three dimensional memory arrays
    54.
    发明授权
    Three dimensional memory arrays 有权

    公开(公告)号：US10461125B2

    公开(公告)日：2019-10-29

    申请号：US15689155

    申请日：2017-08-29

    Applicant: Micron Technology, Inc.

    Inventor： Agostino Pirovano ,  Andrea Redaelli ,  Fabio Pellizzer ,  Innocenzo Tortorelli

    IPC: H01L27/24 ,  H01L45/00 ,  H01L27/115

    Abstract: In an example, a memory array may include a plurality of first dielectric materials and a plurality of stacks, where each respective first dielectric material and each respective stack alternate, and where each respective stack comprises a first conductive material and a storage material. A second conductive material may pass through the plurality of first dielectric materials and the plurality of stacks. Each respective stack may further include a second dielectric material between the first conductive material and the second conductive material.

    Constructions comprising stacked memory arrays
    55.
    发明授权
    Constructions comprising stacked memory arrays 有权

    公开(公告)号：US10396127B2

    公开(公告)日：2019-08-27

    申请号：US16103032

    申请日：2018-08-14

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Redaelli

    IPC: H01L27/24 ,  G11C13/00 ,  H01L45/00

    Abstract: Some embodiments include a construction having a first memory array deck and a second memory array deck over the first memory array deck. The second memory array deck differs from the first memory array deck in one or more operating characteristics, in pitch, and/or in one or more structural parameters; with the structural parameters including different materials and/or different thicknesses of materials. Some embodiments include a construction having a first series and a third series of access/sense lines extending along a first direction, and a second series of access/sense lines between the first and third series and extending along a second direction which crosses the first direction. First memory cells are between the first and second series of access/sense lines and arranged in a first memory array deck. Second memory cells are between the second and third series of access/sense lines and arranged in a second memory array deck.

    Fuses, and Methods of Forming and Using Fuses
    57.
    发明申请
    Fuses, and Methods of Forming and Using Fuses 审中-公开

    公开(公告)号：US20190237284A1

    公开(公告)日：2019-08-01

    申请号：US16375701

    申请日：2019-04-04

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Redaelli ,  Giorgio Servalli

    IPC: H01H85/06 ,  H01H85/11 ,  H01H85/08 ,  G11C13/00 ,  H01H37/32

    CPC classification number: H01H85/06 ,  G11C13/0004 ,  H01H37/32 ,  H01H85/08 ,  H01H85/11 ,  Y10T29/49107

    Abstract: Some embodiments include a fuse having a tungsten-containing structure directly contacting an electrically conductive structure. The electrically conductive structure may be a titanium-containing structure. An interface between the tungsten-containing structure and the electrically conductive structure is configured to rupture when current through the interface exceeds a predetermined level. Some embodiments include a method of forming and using a fuse. The fuse is formed to have a tungsten-containing structure directly contacting an electrically conductive structure. An interface between the tungsten-containing structure and the electrically conductive structure is configured to rupture when current through the interface exceeds a predetermined level. Current exceeding the predetermined level is passed through the interface to rupture the interface.

    Apparatuses including memory cells and methods of operation of same
    60.
    发明授权
    Apparatuses including memory cells and methods of operation of same 有权

    公开(公告)号：US10157670B2

    公开(公告)日：2018-12-18

    申请号：US15338154

    申请日：2016-10-28

    Applicant: Micron Technology, Inc.

    Inventor： Agostino Pirovano ,  Innocenzo Tortorelli ,  Andrea Redaelli ,  Fabio Pellizzer

    IPC: G11C11/00 ,  G11C13/00

    Abstract: Disclosed herein is a memory cell including a memory element and a selector device. The memory cell may be programmed with a programming pulse having a first polarity and read with a read pulse having a second polarity. The memory cell may be programmed with a programming pulse having first and second portions. The first and second portions may have different magnitudes and polarities. The memory cell may exhibit reduced voltage drift and/or threshold voltage distribution. Described herein is a memory cell that acts as both a memory element and a selector device. The memory cell may be programmed with a programming pulse having first and second portions. The first and second portions may have different magnitudes and polarities.

Patent Agency Ranking