公开(公告)号：US20200349999A1

公开(公告)日：2020-11-05

申请号：US16399283

申请日：2019-04-30

Applicant: Micron Technology, Inc.

Inventor： Christopher J. Kawamura ,  Charles L. Ingalls ,  Tae H. Kim

IPC: G11C11/408 ,  G11C11/4076

Abstract: An apparatus includes a plurality of main word line circuits. Each main word line circuit drives a respective global word line to one of an active state value, an intermediate voltage state, or a pre-charge state. The intermediate voltage state voltage is below the active state voltage and above the pre-charge state voltage. The memory device also includes a plurality of sub-word line drivers. Each sub-word line driver is connected to a corresponding global word line and configured to drive a respective local word line between the corresponding global word line voltage and a low voltage value. The apparatus further includes a plurality of phase drivers. Each phase driver is connected to a predetermined number of sub-word line drivers, where each of the predetermined number of sub-word line drivers connects to a different global word line.

公开(公告)号：US20200349998A1

公开(公告)日：2020-11-05

申请号：US16399235

申请日：2019-04-30

Applicant: Micron Technology, Inc.

Inventor： Tae H. Kim ,  Christopher J. Kawamura

IPC: G11C11/408 ,  G11C11/4076

Abstract: A main word line circuit provides a first and second row factor signals. The main word line circuit includes a pull-up circuit to drive a global word line to follow a first decoded address signal when the first row factor signal is at a first value. The main word line circuit includes an intermediate voltage circuit to drive the global word line to follow a value of the second row factor signal. A processing device drives the global word line to an active state by setting the first row factor signal to the first value when the first decoded address signal is at a high state, and drives the global word line to follow a value of the second row factor signal by setting the first row factor signal to the second value while the first decoded address signal is at the high state.

公开(公告)号：US10818342B2

公开(公告)日：2020-10-27

申请号：US16105631

申请日：2018-08-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Christopher J. Kawamura ,  Scott J. Derner

IPC: G11C11/24 ,  G11C11/4091 ,  G11C7/06 ,  G11C11/403 ,  G11C11/4094 ,  G11C11/4097 ,  H01L27/108 ,  G11C5/02 ,  G11C7/18 ,  G11C8/16 ,  G11C11/4096

Abstract: Apparatuses and methods are disclosed that include two transistor-one capacitor memory and for accessing such memory. An example apparatus includes a capacitor coupled to first and second selection components. The apparatus further includes a first digit line and the first selection component configured to couple a first plate of the capacitor to the first digit line, and also includes a second digit line and the second selection component configured to couple the second plate to the second digit line. A sense amplifier is coupled to the second digit line and is configured to amplify a voltage difference between a voltage coupled to the second digit line and the reference voltage.

公开(公告)号：US20180358083A1

公开(公告)日：2018-12-13

申请号：US16105631

申请日：2018-08-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Christopher J. Kawamura ,  Scott J. Derner

IPC: G11C11/4091 ,  H01L27/108 ,  G11C11/4097 ,  G11C11/4094 ,  G11C11/403 ,  G11C7/06 ,  G11C5/02 ,  G11C7/18 ,  G11C11/4096 ,  G11C8/16

Abstract: Apparatuses and methods are disclosed that include two transistor-one capacitor memory and for accessing such memory. An example apparatus includes a capacitor coupled to first and second selection components. The apparatus further includes a first digit line and the first selection component configured to couple a first plate of the capacitor to the first digit line, and also includes a second digit line and the second selection component configured to couple the second plate to the second digit line. A sense amplifier is coupled to the second digit line and is configured to amplify a voltage difference between a voltage coupled to the second digit line and the reference voltage.

公开(公告)号：US20180061471A1

公开(公告)日：2018-03-01

申请号：US15679032

申请日：2017-08-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Christopher J. Kawamura ,  Scott J. Derner

IPC: G11C11/22 ,  G11C11/4091 ,  H01L27/11504

CPC classification number: G11C11/2275 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/2293 ,  G11C11/2297 ,  G11C11/4091 ,  G11C11/5657 ,  H01L27/11504 ,  H01L27/11507 ,  H01L27/11509

Abstract: Apparatuses and methods are disclosed that include ferroelectric memory and for accessing ferroelectric memory. An example method includes increasing a voltage of a first cell plate of a capacitor to change the voltage of a second cell plate of the capacitor, a second digit line, and a second sense node. The voltage of the second cell plate and the second digit line is decreased to change the voltage of the first cell plate, a first digit line, and a first sense node. The first node is driven to a first voltage and the second node is driven to a second voltage responsive to the voltage of the first node being greater than the second node. The first node is driven to the second voltage and the second node is driven to the first voltage responsive to the voltage of the first node being less than the second node.