公开(公告)号：US20220365684A1

公开(公告)日：2022-11-17

申请号：US17302851

申请日：2021-05-13

Applicant: Micron Technology, Inc.

Inventor： Zhongguang Xu ,  Zhenlei Shen ,  Tingjun Xie ,  Seungjune Jeon ,  Murong Lang ,  Zhenming Zhou

IPC: G06F3/06 ,  G06F11/30 ,  G06F11/07

Abstract: Respective life expectancies of a first data unit and a second data unit of the memory device is obtained. A first initial age value corresponding to the first data unit and a second initial age value corresponding to the second data unit are determined. A lower one of the first initial age value and the second initial age value is identified. A first media management operation on a corresponding one of the first data unit or the second data unit associated with the lower one of the first initial age value and the second initial age value is performed. A second media management operation on the first data unit and the second data unit is performed.

公开(公告)号：US20220137854A1

公开(公告)日：2022-05-05

申请号：US17088280

申请日：2020-11-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Murong Lang ,  Jian Huang ,  Zhongguang Xu ,  Zhenming Zhou

IPC: G06F3/06

Abstract: An operation timing condition associated with a memory device to be installed at a memory sub-system is determined. The memory device can include a cross-point array of non-volatile memory cells. The operation timing condition corresponds to a first operation delay timing margin setting for the cross-point array of non-volatile memory cells. A first set of memory access operations is performed at the cross-point array of non-volatile memory cells according to a second operation delay timing margin setting that is lower than the first operation delay timing margin setting. A first number of errors that occurred during performance of the first set of memory access operations is determined. In response to a determination that the first number of errors satisfies an error condition, a first quality rating is assigned for the memory device. In response to a determination that the first number of errors does not satisfy the error criterion, further testing is performed for the cross-point array of non-volatile memory cells based on one or more power level settings.

公开(公告)号：US20220066924A1

公开(公告)日：2022-03-03

申请号：US17005164

申请日：2020-08-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Mikai Chen ,  Zhenlei Shen ,  Murong Lang ,  Zhenming Zhou

IPC: G06F12/02 ,  G06F11/07 ,  G06F11/30

Abstract: A processing device of a memory sub-system performs an operation including obtaining, at a first time, a first scaling factor for a data unit of a set of data units of a memory device. The first scaling factor is associated with a first number of write operations performed at the data unit and a first number of read operations performed at the data unit. The processing device also performs an operation including calculating a first media management metric based on at least the first scaling factor, the first number of write operations, and the first number of read operations. In response to determining that the first media management metric satisfies a media management criterion, the processing device performs a media management operation on the data unit.

公开(公告)号：US11127481B1

公开(公告)日：2021-09-21

申请号：US16926167

申请日：2020-07-10

Applicant: Micron Technology, Inc.

Inventor： Murong Lang ,  Zhongguang Xu ,  Zhenming Zhou

IPC: G11C29/50 ,  G06F11/10 ,  G11C29/12 ,  G06F11/07 ,  G11C29/44

Abstract: A value corresponding to an operating characteristic of a memory sub-system is determined. The value is compared to a first threshold level to determine whether a first condition is satisfied. The value is also compared to a second threshold level to determine whether a second condition is satisfied. In response to satisfying the first condition, a read scrub operation associated with the memory sub-system is executed. In response to satisfying the second condition, a write scrub operation associated with the memory sub-system is executed.

公开(公告)号：US20210065824A1

公开(公告)日：2021-03-04

申请号：US17035501

申请日：2020-09-28

Applicant: Micron Technology, Inc.

Inventor： Zhenming Zhou ,  Murong Lang

IPC: G11C16/34 ,  G11C16/26 ,  G11C16/14 ,  G11C16/30 ,  G11C16/10 ,  G11C13/00 ,  G11C29/50

Abstract: A current demarcation voltage is determined, where the current demarcation voltage is to be applied to a memory cell for reading a state of the memory cell. Based on the current demarcation voltage and a space between a first threshold voltage distribution corresponding to a first state of the memory cell and a second threshold voltage distribution corresponding to a second state of the memory cell, a test demarcation voltage having a low error rate of reading the state of the memory cell is selected. The current demarcation voltage is set to correspond to the selected test demarcation voltage.

公开(公告)号：US20250138996A1

公开(公告)日：2025-05-01

申请号：US18383712

申请日：2023-10-25

Applicant: Micron Technology, Inc.

Inventor： Li-Te Chang ,  Charles S. Kwong ,  Wei Wang ,  Murong Lang ,  Shenming Zhou

IPC: G06F12/02

Abstract: Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to perform adaptive read level threshold voltage operations. The controller determines a first read level offset associated with reading a first set of data from a first level using a first read level of a plurality of read levels. The controller applies the first read level offset to a machine learning model to estimate a second read level offset, associated with reading a second set of data from a second level of the plurality of levels, using a second read level of the plurality of read levels. The controller updates, based on the first read level offset and the estimated second read level offset, a look-up table that includes a set of read level offsets used to read data from the plurality of levels of the individual component.

公开(公告)号：US12272418B2

公开(公告)日：2025-04-08

申请号：US18242884

申请日：2023-09-06

Applicant: Micron Technology, Inc.

Inventor： Zhongguang Xu ,  Zhenlei Shen ,  Murong Lang

IPC: G11C16/34 ,  G06F3/06 ,  G11C29/50

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising receiving, from a host system, an enhanced erase command referencing a block; performing a lookup to determine whether the block is marked in a grown bad block (GBB) data structure used to track blocks that have a defective select gate; and responsive to determining that the block is marked in the GBB data structure, discarding the enhanced erase command.

公开(公告)号：US20250061928A1

公开(公告)日：2025-02-20

申请号：US18936298

申请日：2024-11-04

Applicant: Micron Technology, Inc.

Inventor： Murong Lang ,  Zhenming Zhou ,  Jian Huang ,  Zhongguang Xu ,  Jiangli Zhu

IPC: G11C7/10

Abstract: A read operation is performed on a set of memory cells addressable by a first wordline (WL), wherein the set of memory cells is comprised by an open translation unit (TU_ of memory cells of a memory device. Respective threshold voltage offset bins for each WL of a second plurality of WLs coupled to respective sets of memory cells comprised by the open TU are determined based on a threshold voltage offset bin associated with the first WL. Respective default threshold voltages for each WL of the first plurality of WLs are updated based on the respective threshold voltage offset bins for each WL of the second plurality of WLs.

公开(公告)号：US20250036307A1

公开(公告)日：2025-01-30

申请号：US18912242

申请日：2024-10-10

Applicant: Micron Technology, Inc.

Inventor： Murong Lang ,  Christina Papagianni ,  Zhenming Zhou ,  Ting Luo

IPC: G06F3/06

Abstract: Methods, systems, and devices for cross-temperature mitigation in a memory system are described. A memory system may determine a first temperature of the memory system. Based on the first temperature satisfying a first threshold, the memory system may write a set of data to a first block of the memory system that is configured with a first rate for performing scan operations to determine error information for the first block. The memory system may then determine a second temperature of the memory system after writing the set of data to the first block. Based on the second temperature satisfying a second threshold, the memory system may transfer the set of data to a second block of the memory system that is configured with a second rate for performing scan operations to determine error information for the second block.

公开(公告)号：US20250004663A1

公开(公告)日：2025-01-02

申请号：US18751673

申请日：2024-06-24

Applicant: Micron Technology, Inc.

Inventor： Christina Papagianni ,  Murong Lang ,  Zhenming Zhou

IPC: G06F3/06

Abstract: Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to provide adaptive media management based on temperature-related memory component capabilities. The controller determines a read disturb condition criterion associated with an individual memory component of a set of memory components and determines a temperature of a memory sub-system comprising the set of memory components. The controller adjusts the read disturb condition criterion based on the temperature and program erase cycles (PEC) of the memory sub-system and performs an individual media management operation on the individual memory component in response to determining that the adjusted read disturb condition criterion has been satisfied.