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公开(公告)号：US10910038B2
公开(公告)日：2021-02-02
申请号：US16399283
申请日：2019-04-30
Applicant: Micron Technology, Inc.
Inventor： Christopher J. Kawamura , Charles L. Ingalls , Tae H. Kim
IPC: G11C5/14 , G11C11/408 , G11C11/4076
Abstract: An apparatus includes a plurality of main word line circuits. Each main word line circuit drives a respective global word line to one of an active state value, an intermediate voltage state, or a pre-charge state. The intermediate voltage state voltage is below the active state voltage and above the pre-charge state voltage. The memory device also includes a plurality of sub-word line drivers. Each sub-word line driver is connected to a corresponding global word line and configured to drive a respective local word line between the corresponding global word line voltage and a low voltage value. The apparatus further includes a plurality of phase drivers. Each phase driver is connected to a predetermined number of sub-word line drivers, where each of the predetermined number of sub-word line drivers connects to a different global word line.
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公开(公告)号：US20200349990A1
公开(公告)日：2020-11-05
申请号：US16399159
申请日：2019-04-30
Applicant: Micron Technology, Inc.
Inventor： Charles L. Ingalls , Tae H. Kim
IPC: G11C8/08 , G11C11/408
Abstract: A FX phase driver for a memory device having a first driver circuit including a first pull-up circuit configured to drive a first phase signal to a first high state value and a first pull-down circuit configured to drive the first phase signal to a first low state value. The phase driver also including a second driver circuit including a second pull-up circuit configured to drive a second phase signal to a second high state value that is higher than an active state voltage level of a word line in the memory device and a second pull-down circuit configured to drive the second phase signal to a second low state value. The second pull-down circuit includes a stabilization circuit configured to provide a resistive path for a leakage current in the second pull-down circuit when the second pull-up circuit drives the second phase signal to the second high state value.
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公开(公告)号：US20200098400A1
公开(公告)日：2020-03-26
申请号：US16696246
申请日：2019-11-26
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Tae H. Kim , Byung S. Moon
Abstract: Methods and apparatuses are provided for driver circuits without voltage level shifters. An example apparatus includes a semiconductor device including a row decoder circuit that includes a driver circuit and a switching circuit. The driver circuit is configured to receive an input signal having a first logical value, a first voltage signal, and a configurable power signal. The driver circuit is further configured to provide an output signal having the first logical value based on the first signal having the first logical value. A voltage level of the input signal is based on the first voltage signal and a voltage level the output signal is based on the configurable voltage signal. The switching circuit is configured to receive the first voltage signal and a second voltage signal and to provide the configurable voltage signal having a voltage level of one of the first voltage signal or the second voltage signal.
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公开(公告)号：US20190259444A1
公开(公告)日：2019-08-22
申请号：US16234319
申请日：2018-12-27
Applicant: Micron Technology, Inc.
Inventor： Tae H. Kim , Sangmin Hwang , Si-Woo Lee
IPC: G11C11/4091 , G11C11/22 , G11C11/4097
Abstract: Some embodiments include an apparatus having first and second comparative bitlines extending horizontally and coupled with a sense amplifier. First memory cell structures are coupled with the first comparative bitline. Each of the first memory cell structures has a first transistor associated with a first capacitor. Second memory cell structures are coupled with the second comparative bitline. Each of the second memory cell structures has a second transistor associated with a second capacitor. Each of the first capacitors has a container-shaped first node and is vertically offset from an associated first sister capacitor which is a mirror image of its associated first capacitor along a horizontal plane. Each of the second capacitors has a container-shaped first node and is vertically offset from an associated second sister capacitor which is a mirror image of its associated second capacitor along the horizontal plane.
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公开(公告)号：US10311927B2
公开(公告)日：2019-06-04
申请号：US15495401
申请日：2017-04-24
Applicant: Micron Technology, Inc.
Inventor： Tae H. Kim
Abstract: Methods and apparatuses of providing word line voltages are disclosed. An example method includes: activating and deactivating a word line. Activating the word line includes: rendering the first, second and third transistors conductive, non-conductive and non-conductive, respectively, wherein the first transistor is rendered conductive by supplying a gate of the first transistor with a first voltage; and supplying the first node with an active voltage. Deactivating the word line includes: changing a voltage of the first node from the active voltage to an inactive voltage; changing a voltage of the gate of the first transistor from the first voltage to a second voltage, wherein the first transistor is kept conductive by the second voltage; rendering the third transistor conductive during the gate of the first transistor being at the second voltage; and rendering the first and second transistors non-conductive and conductive, respectively, after the third transistor has been rendered conductive.
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Patent Agency Ranking
公开(公告)号：US20190027204A1
公开(公告)日：2019-01-24
申请号：US15655675
申请日：2017-07-20
Applicant: Micron Technology, Inc.
Inventor： Tae H. Kim , Corrado Villa
CPC classification number: G11C11/2297 , G06F1/3275 , G06F1/3287 , G06F1/3296 , G11C11/221 , G11C11/2255 , G11C11/2257 , G11C11/2273 , G11C11/2275
Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. An electronic memory device may include a plurality of plate portions separated by a plurality of segmentation lines, which may be oriented in a plane parallel to rows of a memory array or columns of the memory array, or both. The segmented plate may be employed instead of a single plate for the array. The one or more plate portions may be energized during access operations of a ferroelectric cell in order to create a voltage different across the cell or to facilitate changing the charge of the cell. Each of the plate portions may include one or more memory cells. The memory cells on a plate portion may be read from or written to after the plate portion is activated by a plate driver.
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公开(公告)号：US20150117124A1
公开(公告)日：2015-04-30
申请号：US14068940
申请日：2013-10-31
Applicant: Micron Technology, Inc.
Inventor： Scott J. Derner , Charles L. Ingalls , Howard Kirsch , Tae H. Kim
Abstract: Some embodiments include apparatuses and methods having a first data line, a second data line, a first transistor, a sense amplifier, and a circuit. The first transistor can operate to couple the first data line to a first node during a first stage of an operation of obtaining information from a memory cell associated with the first data line. The second transistor can operate to couple the second data line to a second node during the first stage. The circuit can operate to apply a first signal to a gate of the first transistor during the operation and to apply a second signal to a gate of the second transistor during the operation. The sense amplifier can operate to perform a sense function on the first and second data lines during a second stage of the operation. Additional apparatus and methods are described.
Abstract translation: 一些实施例包括具有第一数据线，第二数据线，第一晶体管，读出放大器和电路的装置和方法。 在从与第一数据线相关联的存储器单元获得信息的操作的第一阶段期间，第一晶体管可以操作以将第一数据线耦合到第一节点。 第二晶体管可以在第一阶段期间将第二数据线耦合到第二节点。 电路可操作以在操作期间将第一信号施加到第一晶体管的栅极，并且在操作期间将第二信号施加到第二晶体管的栅极。 感测放大器可以在操作的第二阶段期间操作以在第一和第二数据线上执行感测功能。 描述附加的装置和方法。
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公开(公告)号：US12051460B2
公开(公告)日：2024-07-30
申请号：US17447490
申请日：2021-09-13
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Tae H. Kim , Christopher J. Kawamura , Jiyun Li
IPC: G11C7/12 , G11C7/06 , G11C11/4091 , G11C11/4094 , G11C11/4097 , G11C11/4074
CPC classification number: G11C11/4091 , G11C7/06 , G11C11/4094 , G11C11/4097 , G11C7/12 , G11C11/4074 , G11C2207/002 , G11C2207/005
Abstract: Apparatuses, systems, and methods for single-ended sense amplifiers. A memory device may include a number of sense amplifiers used to read the voltage of memory cells along digit lines. Double-ended sense amplifiers are coupled to two digit lines. Single-ended sense amplifiers are coupled to a single digit line. The memory cells of an edge word line of a memory array may alternately be coupled to a single-ended sense amplifier or a double-ended sense amplifier. The use of single-ended sense amplifiers may reduce a footprint for a given number of memory cells in the array.
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59.发明公开公开(公告)号：US20230360690A1
公开(公告)日：2023-11-09
申请号：US17662198
申请日：2022-05-05
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Jiyun Li , Christopher J. Kawamura , Tae H. Kim
IPC: G11C11/4091
CPC classification number: G11C11/4091 , H03F3/45264
Abstract: Apparatuses, systems, and methods for compensated sense amplifier with crosscoupled n-type transistors. A sense amplifier has a pair of p-type transistors coupled between a system voltage and respective first and second gut nodes. When a command signal is active, the p-type transistors are coupled in a diode fashion from the system voltage to the respective gut nodes. The amplifier also has a pair of n-type transistors which are cross coupled, where a first n-type transistor has a node coupled to the first gut node and a gate coupled to the second gut node and the second n-type transistor has a node coupled to the second gut node and a gate coupled to the first gut node. Each of the n-type transistors may have a separate current flowing through them and respective one of a pair of feedback transistors to a ground voltage.
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公开(公告)号：US20230084668A1
公开(公告)日：2023-03-16
申请号：US17447490
申请日：2021-09-13
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Tae H. Kim , Christopher J. Kawamura , Jiyun Li
IPC: G11C11/4091
Abstract: Apparatuses, systems, and methods for single-ended sense amplifiers. A memory device may include a number of sense amplifiers used to read the voltage of memory cells along digit lines. Double-ended sense amplifiers are coupled to two digit lines. Single-ended sense amplifiers are coupled to a single digit line. The memory cells of an edge word line of a memory array may alternately be coupled to a single-ended sense amplifier or a double-ended sense amplifier. The use of single-ended sense amplifiers may reduce a footprint for a given number of memory cells in the array.
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