公开(公告)号：US20220004517A1

公开(公告)日：2022-01-06

申请号：US17360994

申请日：2021-06-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Matthew B. Leslie ,  Timothy M. Hollis ,  Roy E. Greeff

IPC: G06F13/42 ,  G06F13/16 ,  G06F1/08 ,  G11C8/18 ,  G11C8/06

Abstract: Methods, systems, and apparatuses related to configured dual register clock driver (RCD) devices on a single memory subsystem using different configuration information are described. In some examples, configuration of the two RCD devices with different configuration information may include use of a serial data bus to receive and store first RCD configuration data, which is provided to both of the RCD devices to configure one or more parameters of each respective RCD device. One of the RCD devices may receive second configuration data via a command and address bus to independently update the one or more configuration parameters of one of the two RCD devices.

公开(公告)号：US20210241810A1

公开(公告)日：2021-08-05

申请号：US17164738

申请日：2021-02-01

Applicant: Micron Technology, Inc.

Inventor： Timothy M. Hollis ,  James S. Rehmeyer ,  Baekkyu Choi ,  Yogesh Sharma ,  Eric J. Stave ,  Brian W. Huber ,  Miles S. Wiscombe

IPC: G11C11/406

Abstract: Methods, systems, and devices for voltage adjustment based on, for example, pending refresh operations are described. A memory device may periodically perform refresh operations to refresh volatile memory cells and may at times postpone performing one or more refresh operations. A memory device may determine a quantity of pending (e.g., postponed) refresh operations, such as by determining a quantity of refresh intervals that have elapsed without receiving or executing a refresh command, among other methods. A memory device may pre-emptively adjust (or cause to be adjusted) a supply voltage associated with the memory device or memory device component based on the quantity of pending refresh operations to prepare for the current demand associated with the performing the one or more pending refresh operations. For example, the memory device may increase a supply voltage associated with one or more components to prepare for performing multiple pending refresh operations.

公开(公告)号：US20200327057A1

公开(公告)日：2020-10-15

申请号：US16912434

申请日：2020-06-25

Applicant: Micron Technology, Inc.

Inventor： Robert Nasry Hasbun ,  Timothy M. Hollis ,  Jeffrey P. Wright ,  Dean D. Gans

IPC: G06F12/0806 ,  H04L5/00

Abstract: Methods, systems, and devices that support variable modulation schemes for memory are described. A device may switch between different modulation schemes for communication based on one or more operating parameters associated with the device or a component of the device. The modulation schemes may involve amplitude modulation in which different levels of a signal represent different data values. For instance, the device may use a first modulation scheme that represents data using two levels and a second modulation scheme that represents data using four levels. In one example, the device may switch from the first modulation scheme to the second modulation scheme when bandwidth demand is high, and the device may switch from the second modulation scheme to the first modulation scheme when power conservation is in demand. The device may also, based on the operating parameter, change the frequency of the signal pulses communicated using the modulation schemes.

公开(公告)号：US10447512B2

公开(公告)日：2019-10-15

申请号：US15885536

申请日：2018-01-31

Applicant: Micron Technology, Inc.

Inventor： Feng Lin ,  Timothy M. Hollis

IPC: G11C7/20 ,  H04L7/00 ,  H04L25/03 ,  H04L25/49 ,  G11C7/10

Abstract: A memory interface may include a transmitter that generates multi-level signals made up of symbols that convey multiple bits of data. The transmitter may include a first data path for a first bit (e.g., a least significant bit (LSB)) in a symbol and a second data path for a second bit (e.g., the most significant bit (MSB)) in the symbol. Each path may include a de-emphasis or pre-emphasis buffer circuit that inverts and delays signals received at the de-emphasis or pre-emphasis buffer circuit. The delayed and inverted data signals may control de-emphasis or pre-emphasis drivers that are configured to apply de-emphasis or pre-emphasis to a multi-level signal.

公开(公告)号：US10425260B2

公开(公告)日：2019-09-24

申请号：US15854600

申请日：2017-12-26

Applicant: Micron Technology, Inc.

Inventor： Timothy M. Hollis ,  Markus Balb ,  Ralf Ebert

IPC: H04L25/49 ,  G11C7/10

Abstract: Techniques are provided herein to increase a rate of data transfer across a large number of channels in a memory device using multi-level signaling. Such multi-level signaling may be configured to increase a data transfer rate without increasing the frequency of data transfer and/or a transmit power of the communicated data. An example of multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the multi-level signal may be configured to represent a plurality of bits of data.

公开(公告)号：US20190287583A1

公开(公告)日：2019-09-19

申请号：US16058566

申请日：2018-08-08

Applicant: Micron Technology, Inc.

Inventor： Timothy M. Hollis

IPC: G11C7/10 ,  H01L25/065 ,  H01L23/48 ,  G11C7/22 ,  G06F13/16

Abstract: Methods, systems, and apparatuses for a memory device that is configurable based on the type of substrate used to couple the memory device with a host device are described. The reconfigurable memory device may include a plurality of components for different configurations. Various components of the reconfigurable memory die may be activated/deactivated based on a type of substrate used in the memory device. The memory device may include an input/output (I/O) interface that is variously configurable. A first configuration may cause the memory device to communicate signals modulated using a first modulation scheme across a channel of a first width. A second configuration may cause the memory device to communicate signals modulated using a second modulation scheme across a channel of a second width. The I/O interface may include one or more switching components to selectively couple pins of a channel together and/or selectively couple components to various pins.

公开(公告)号：US20190273640A1

公开(公告)日：2019-09-05

申请号：US16415512

申请日：2019-05-17

Applicant: Micron Technology, Inc.

Inventor： Feng Lin ,  Timothy M. Hollis

IPC: H04L25/49 ,  G11C7/20 ,  H04L7/00 ,  H04L25/03 ,  G11C7/10

Abstract: A memory interface may include a transmitter that generates multi-level signals made up of symbols that convey multiple bits of data. The transmitter may include a first data path for a first bit (e.g., a least significant bit (LSB)) in a symbol and a second data path for a second bit (e.g., the most significant bit (MSB)) in the symbol. Each path may include a de-emphasis or pre-emphasis buffer circuit that inverts and delays signals received at the de-emphasis or pre-emphasis buffer circuit. The delayed and inverted data signals may control de-emphasis or pre-emphasis drivers that are configured to apply de-emphasis or pre-emphasis to a multi-level signal.

公开(公告)号：US10381050B2

公开(公告)日：2019-08-13

申请号：US15855849

申请日：2017-12-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Timothy M. Hollis ,  Dean D. Gans ,  Larren G. Weber

IPC: G11C8/00 ,  G11C5/14 ,  G11C7/10 ,  G11C11/4093 ,  G11C11/4096

Abstract: An apparatus comprising is disclosed. The apparatus a driver circuit configured to selectively provide a first supply voltage to an output node in a first operating mode and to selectively provide a second supply voltage to the output node in a second operating mode, based on one or more enable signals.

公开(公告)号：US10353668B2

公开(公告)日：2019-07-16

申请号：US15431421

申请日：2017-02-13

Applicant: Micron Technology, Inc.

Inventor： Timothy M. Hollis

IPC: G06F5/06 ,  G06F13/38 ,  G06F13/42 ,  H04L12/40 ,  H04L25/02 ,  H04L29/08

Abstract: Methods and apparatuses to transfer data between a first device and a second device are disclosed. In various embodiments, an apparatus includes a first device and a second device. The first device includes at least one first non-differential transmitter coupled to a first channel, at least one second non-differential transmitter coupled to a second channel, and at least one differential receiver to receive a data bit and its complement on the first and second channels in parallel. The second device includes at least one first non-differential receiver coupled to the first channel, at least one second non-differential receiver coupled to the second channel, and at least one differential transmitter to transmit a data bit and its complement on the first and second channels in parallel. Other methods and apparatuses are disclosed.

公开(公告)号：US10297294B2

公开(公告)日：2019-05-21

申请号：US15703365

申请日：2017-09-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Timothy M. Hollis ,  Huy T. Vo ,  Dirgha Khatri

IPC: G11C7/10 ,  G11C7/22 ,  G11C5/04

Abstract: Apparatuses, memory modules, and methods for performing intra-module data bus inversion operations are described. An example apparatus include a memory module comprising a data bus inversion (DBI) and buffer circuit and a plurality of memories. The DBI and buffer circuit configured to encode a block of data received by the memory module and to provide DBI data and a corresponding DBI bit to a respective memory of the plurality of memories.