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    Method and system for enhanced read performance in low pin count interface
    51.
    发明授权
    Method and system for enhanced read performance in low pin count interface 有权

    公开(公告)号：US11302366B2

    公开(公告)日：2022-04-12

    申请号：US17070340

    申请日：2020-10-14

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Kuen-Long Chang ,  Su-Chueh Lo ,  Yung-Feng Lin

    IPC: G11C7/10 ,  G11C7/22 ,  G06F9/445 ,  G06F9/38

    Abstract: A memory device supporting multi-address read operations improves throughput on a bi-directional serial port. The device includes a memory array and an input/output port having an input mode and an output mode. The input/output port has at least one signal line used alternately in both the input and output modes. A controller includes logic configured to execute a multi-address read operation in response to receiving a read command on the input/output port in the input mode, the multi-address read operation including receiving a first address and a second address using the at least one signal line in the input mode before switching to the output mode, switching to the output mode and outputting data identified by the first address using the at least one signal line.

    Security memory scheme
    52.
    发明授权
    Security memory scheme 有权

    公开(公告)号：US11050569B2

    公开(公告)日：2021-06-29

    申请号：US16541009

    申请日：2019-08-14

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Chia-Jung Chen ,  Chin-Hung Chang ,  Kuen-Long Chang

    IPC: H04L29/06 ,  H04L9/32 ,  G06F3/06

    Abstract: A memory device can include a memory, and an interface to receive a memory command sequence. A message authentication code MAC is provided with the command sequence. Control circuits on the device include a command decoder to decode a received command sequence and to execute an identified memory operation. A message authentication engine includes logic to compute a value of a message authentication code to be matched with the received message authentication code based on the received command sequence and a stored key. The device can store a plurality of keys associated with one or more memory zones in the memory. Logic on the device prevents completion of the memory operation identified by the command sequence if the value computed does not match the received message authentication code.

    I/O bus shared memory system
    53.
    发明授权
    I/O bus shared memory system 有权

    公开(公告)号：US10884956B2

    公开(公告)日：2021-01-05

    申请号：US15215439

    申请日：2016-07-20

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Kuen-Long Chang ,  Ken-Hui Chen ,  Chin-Hung Chang

    IPC: G06F13/16 ,  G06F13/42

    Abstract: A memory system has a plurality of memory devices coupled with a hub in discrete and shared port arrangements. A plurality of bus lines connect the plurality of memory devices to the hub, including a first subset of bus lines connected in a point-to-point configuration between the hub and a particular memory device, and a second subset of bus lines connected to all the memory devices in the plurality of memory devices including the particular memory device. Bus operation logic is configured to use the first subset of bus lines in a first operation accessing the particular memory device while simultaneously using the second subset of bus lines in a second operation accessing a different selected memory device of the plurality of memory devices.

    Physical unclonable function for security key
    54.
    发明授权
    Physical unclonable function for security key 有权

    公开(公告)号：US10680809B2

    公开(公告)日：2020-06-09

    申请号：US15984685

    申请日：2018-05-21

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Kuen-Long Chang ,  Ken-Hui Chen ,  Chin-Hung Chang

    IPC: G06F11/30 ,  H04L9/08

    Abstract: A system including a host and a guest device, where the guest device can be implemented on a single packaged integrated circuit or a multichip circuit and have logic to use a physical unclonable function to produce a security key. The device can include logic on the guest to provide the PUF key to the host in a secure manner. The physical unclonable function can use entropy derived from non-volatile memory cells to produce the initial key. Logic is described to disable changes to PUF data, and thereby freeze the key after it is stored in the set.

    Circuit for voltage detection and protection and operating method thereof
    60.
    发明授权
    Circuit for voltage detection and protection and operating method thereof 有权
    电压检测和保护电路及其操作方法

    公开(公告)号：US09490624B2

    公开(公告)日：2016-11-08

    申请号：US14472520

    申请日：2014-08-29

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Yu-Meng Chaung ,  Chun-Hsiung Hung ,  Kuen-Long Chang ,  Ken-Hui Chen

    IPC: H02H3/20 ,  H02H3/24 ,  G11C5/14

    CPC classification number: H02H3/202 ,  G11C5/143 ,  H02H3/20 ,  H02H3/22 ,  H02H3/243 ,  H02H7/22

    Abstract: A circuit for voltage detection and protection comprises a first block, a first voltage detector, a second block and a second voltage detector. The first block receives a first voltage supply. The first voltage detector detects the first voltage supply and generates a first detecting signal when detecting the first voltage supply level is out of the first operating voltage range. The second block receives a second voltage supply. The second voltage detector detects the second voltage supply and generates a second detecting signal when detecting the second voltage supply level is out of the second operating voltage range. The first block performs a protection operation on the circuit when monitoring at least one of the first and second detecting signals.

    Abstract translation: 用于电压检测和保护的电路包括第一块，第一电压检测器，第二块和第二电压检测器。 第一块接收第一个电压源。 第一电压检测器检测第一电压源，并且当检测到第一电压供应电平在第一工作电压范围之外时产生第一检测信号。 第二块接收第二电压源。 第二电压检测器检测第二电压源，并且当检测到第二电压供应电平在第二工作电压范围之外时产生第二检测信号。 当监视第一和第二检测信号中的至少一个时，第一块在电路上执行保护操作。

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