公开(公告)号：US20060017079A1

公开(公告)日：2006-01-26

申请号：US10896421

申请日：2004-07-21

申请人： Srinivasan Chakravarthi ,  Amitabh Jain ,  Xin Zhang

发明人： Srinivasan Chakravarthi ,  Amitabh Jain ,  Xin Zhang

IPC分类号： H01L29/76 ,  H01L21/425 ,  H01L31/117 ,  H01L21/44

CPC分类号： H01L21/26513 ,  H01L21/02667 ,  H01L21/2022 ,  H01L21/26506 ,  H01L29/66575 ,  H01L29/78

摘要： We disclose a process for forming ultra shallow n+p junctions. The junction is formed by, for example, implanting 3E14 ions/cm2 of antimony ions at 5 keV into silicon. The silicon is pre-amorphized by a previous ion-implantation. The pre-amorphizing implant species may be germanium or arsenic. Germanium may be implanted at 15 keV and Arsenic may be implanted at 2 keV. Both the pre-amorphizing implant and the antimony implant are preferably through bare silicon surface—not covered with any foreign material with the exception of possibly a layer of native oxide. The junction is annealed at about 950° C. following the implants to re-crystallize the implanted region and to activate the implanted ions. The ultra shallow junction is superior because it has a abrupt junction, high sheet resistance and can be formed with low thermal budget.

摘要翻译： 我们公开了形成超浅层p + p结的方法。 该结通过例如以5keV将3E14离子/ cm 2的锑离子注入到硅中而形成。 硅通过先前的离子注入而被非晶化。 前非晶化植入物种可以是锗或砷。 锗可以以15keV注入，砷可以以2keV注入。 预非晶化植入物和锑植入物优选通过裸露的硅表面 - 未被任何异物覆盖，除了可能的一层天然氧化物之外。 接合点在大约950℃下退火，在植入物重新结晶植入区域并激活注入的离子之后。 超浅结是优越的，因为其具有突然的接合，高的薄层电阻，并且可以以低的热预算形成。

公开(公告)号：US20050059260A1

公开(公告)日：2005-03-17

申请号：US10810905

申请日：2004-03-26

申请人： Haowen Bu ,  Brian Hornung ,  P.R. Chidambaram ,  Amitabh Jain ,  Rajesh Khamankar ,  Nandu Mahalingam ,  Srinivansan Chakravarthi

发明人： Haowen Bu ,  Brian Hornung ,  P.R. Chidambaram ,  Amitabh Jain ,  Rajesh Khamankar ,  Nandu Mahalingam ,  Srinivansan Chakravarthi

IPC分类号： H01L21/00 ,  H01L21/265 ,  H01L21/3205 ,  H01L21/324 ,  H01L21/336 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/08 ,  H01L29/76 ,  H01L29/78

CPC分类号： H01L21/26506 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/3185 ,  H01L21/324 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/0847 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7845

摘要： The present invention teaches the formation of CMOS transistors using interfacial nitrogen at the interface between the lightly doped extension regions and an overlying insulating layer in combination with a capping layer of silicon nitride, both prior to the final source/drain anneal. Doses and energies may be increased for the P-channel lightly-doped drain, source and drain regions. The resulting transistors exhibit desirably high drive current and low off-state leakage current and overlap capacitance.

摘要翻译： 本发明教导了在最终的源极/漏极退火之前，在轻掺杂的延伸区域之间的界面处的界面氮和与氮化硅覆盖层结合的上覆绝缘层的CMOS晶体管的形成。 P沟道轻掺杂漏极，源极和漏极区域的剂量和能量可能会增加。 所得到的晶体管显示期望的高驱动电流和低截止状态的漏电流和重叠电容。

公开(公告)号：US06808997B2

公开(公告)日：2004-10-26

申请号：US10393749

申请日：2003-03-21

申请人： Amitabh Jain ,  Stephanie W. Butler

发明人： Amitabh Jain ,  Stephanie W. Butler

IPC分类号： H01L21336

CPC分类号： H01L29/6659 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/324 ,  H01L29/1083 ,  H01L29/7833

摘要： Methods are disclosed for forming ultra shallow junctions in semiconductor substrates using multiple ion implantation steps. The ion implantation steps include implantation of at least one electronically-active dopant as well as the implantation of at least two species effective at limiting junction broadening by channeling during dopant implantation and/or by thermal diffusion. Following dopant implantation, the electronically-active dopant is activated by thermal processing.

摘要翻译： 公开了使用多个离子注入步骤在半导体衬底中形成超浅结的方法。 离子注入步骤包括植入至少一种电子活性掺杂剂以及通过在掺杂剂注入期间通过沟槽化和/或通过热扩散来有效地限制结扩展的至少两种物质的注入。 在掺杂剂注入之后，电子活性掺杂剂通过热处理而被激活。

公开(公告)号：US08877581B2

公开(公告)日：2014-11-04

申请号：US12855736

申请日：2010-08-13

申请人： Amitabh Jain ,  Deborah J. Riley

发明人： Amitabh Jain ,  Deborah J. Riley

IPC分类号： H01L29/78 ,  H01L21/8238

CPC分类号： H01L21/823814 ,  H01L21/823807 ,  H01L29/7848

摘要： An integrated circuit (IC) includes a plurality of strained metal oxide semiconductor (MOS) devices that include a semiconductor surface having a first doping type, a gate electrode stack over a portion of the semiconductor surface, and source/drain recesses that extend into the semiconductor surface and are framed by semiconductor surface interface regions on opposing sides of the gate stack. A first epitaxial strained alloy layer (rim) is on the semiconductor surface interface regions, and is doped with the first doping type. A second epitaxial strained alloy layer is on the rim and is doped with a second doping type that is opposite to the first doping type that is used to form source/drain regions.

摘要翻译： 集成电路（IC）包括多个应变金属氧化物半导体（MOS）器件，其包括具有第一掺杂类型的半导体表面，半导体表面的一部分上的栅极电极堆叠以及延伸到 半导体表面并且由栅堆叠的相对侧上的半导体表面界面区域构成。 第一外延应变合金层（边缘）在半导体表面界面区域上，并掺杂有第一掺杂型。 第二外延应变合金层位于边缘上并且掺杂有与用于形成源极/漏极区的第一掺杂类型相反的第二掺杂类型。

公开(公告)号：US08772118B2

公开(公告)日：2014-07-08

申请号：US13484592

申请日：2012-05-31

申请人： Amitabh Jain

发明人： Amitabh Jain

IPC分类号： H01L21/336 ,  H01L21/66

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L22/14 ,  H01L2924/0002 ,  H01L2924/00

摘要： A process of integrated circuit manufacturing includes providing (32, 33) a spacer on a gate stack to provide a horizontal offset over the channel region for otherwise-direct application (34) of a PLDD implant dose in semiconductor, additionally depositing (35) a seal substance to provide a screen thickness vertically while thereby augmenting the spacer on the gate stack to provide an increased offset horizontally from the gate stack and form a horizontal screen free of etch, and subsequently providing (36) an NLDD implant dose for NLDD formation. Various integrated circuit structures, devices, and other processes of manufacture, and processes of testing are also disclosed.

摘要翻译： 集成电路制造的过程包括在栅极叠层上提供（32,33）间隔物，以在沟道区域上提供水平偏移，用于在半导体中另外存储（35）一个PLDD注入剂量的直接应用（34） 密封物质以垂直地提供屏幕厚度，从而增加栅极堆叠上的间隔物，以提供与栅极堆叠水平的增加的偏移，并形成没有蚀刻的水平屏幕，并随后提供（36）用于NLDD形成的NLDD注入剂量。 还公开了各种集成电路结构，装置和其它制造工艺以及测试过程。

公开(公告)号：US08124511B2

公开(公告)日：2012-02-28

申请号：US11951448

申请日：2007-12-06

申请人： Amitabh Jain

发明人： Amitabh Jain

IPC分类号： H01L21/425

CPC分类号： H01L21/26506 ,  H01L21/26513 ,  H01L21/26566 ,  H01L21/2658 ,  H01L21/268 ,  H01L29/6659

摘要： One aspect provides a method of manufacturing a semiconductor device having reduced N/P or P/N junction crystal disorder. In one aspect, this improvement is achieved by forming gate electrodes over a semiconductor substrate, amorphizing the semiconductor substrate that creates amorphous regions adjacent the gate electrodes to a depth in the semiconductor substrate. Source/drains are formed adjacent the gate electrodes by placing conductive dopants in the semiconductor substrate, wherein displaced substrate atoms and the conductive dopants are contained within the depth of the amorphous regions. The semiconductor substrate is annealed to re-crystallize the amorphous regions subsequent to forming the source/drains.

摘要翻译： 一方面提供一种制造具有降低的N / P或P / N结晶体紊乱的半导体器件的方法。 在一个方面，这种改进通过在半导体衬底上形成栅电极来实现，使半导体衬底非晶化，该半导体衬底产生与栅电极相邻的非晶区到达半导体衬底的深度。 源极/漏极通过在半导体衬底中放置导电掺杂剂而形成在栅极附近，其中位移的衬底原子和导电掺杂剂包含在非晶区域的深度内。 在形成源极/漏极之后，半导体衬底被退火以使无定形区域再结晶。

公开(公告)号：US07825025B2

公开(公告)日：2010-11-02

申请号：US10959674

申请日：2004-10-04

申请人： Amitabh Jain ,  Peijun Chen ,  Jorge A. Kittl

发明人： Amitabh Jain ,  Peijun Chen ,  Jorge A. Kittl

IPC分类号： H01L21/44 ,  H01L21/477

CPC分类号： H01L21/28518 ,  H01L21/823807 ,  H01L21/823835 ,  H01L29/665 ,  H01L29/78

摘要： According to one embodiment of the invention, a method for nickel silicidation includes providing a substrate having a source region, a gate region, and a drain region, forming a source in the source region and a drain in the drain region, annealing the source and the drain, implanting, after the annealing the source and the drain, a heavy ion in the source region and the drain region, depositing a nickel layer in each of the source and drain regions, and heating the substrate to form a nickel silicide region in each of the source and drain regions by heating the substrate.

摘要翻译： 根据本发明的一个实施例，一种用于镍硅化的方法包括提供具有源极区，栅极区和漏极区的衬底，在源区中形成源极和在漏极区中形成漏极，退火源和 漏极，在源极和漏极退火之后注入源区域和漏极区域中的重离子，在源极和漏极区域中的每一个中沉积镍层，并加热衬底以形成硅化镍区域 每个源极和漏极区域通过加热衬底。

公开(公告)号：US20100261298A1

公开(公告)日：2010-10-14

申请号：US12757704

申请日：2010-04-09

申请人： Brian K. Kirkpatrick ,  Steven L. Prins ,  Amitabh Jain

发明人： Brian K. Kirkpatrick ,  Steven L. Prins ,  Amitabh Jain

IPC分类号： H01L21/26 ,  H01L21/66

CPC分类号： H01L21/26506 ,  H01L21/02532 ,  H01L21/02658 ,  H01L21/02667 ,  H01L22/12 ,  H01L22/20

摘要： A method for reducing curvature of a wafer having a semiconductor surface. One or more process steps are identified at which wafers exhibit the largest curvature, and/or wafer curvature that may reduce die yield. A crystal damaging process converts at least a portion of the semiconductor surface into at least one amorphous surface region After or contemporaneously with the crystal damaging, the amorphous surface region is recrystallized by recrystallization annealing that anneals the wafer for a time ≦5 seconds at a temperature sufficient for recrystallization of the amorphous surface region. A subsequent photolithography step is facilitated due to the reduction in average wafer curvature provided by the recrystallization.

摘要翻译： 一种用于减小具有半导体表面的晶片的曲率的方法。 识别一个或多个工艺步骤，在该处理步骤中，晶片呈现最大的曲率，和/或晶片曲率，其可以降低模具的产量。 晶体损伤过程将半导体表面的至少一部分转化成至少一个非晶表面区域在晶体损坏之后或同时具有晶体损伤的情况下，非晶表面区域通过重结晶退火重结晶，使晶片退火一段时间， 足以使非晶表面区域再结晶的温度。 由于再结晶提供的平均晶片曲率的减小，随后的光刻步骤变得容易。

公开(公告)号：US20090130864A1

公开(公告)日：2009-05-21

申请号：US11942367

申请日：2007-11-19

申请人： Narendra Singh MEHTA ,  Perry Howard Shields ,  Amitabh Jain

发明人： Narendra Singh MEHTA ,  Perry Howard Shields ,  Amitabh Jain

IPC分类号： H01L21/02 ,  F27D11/00

CPC分类号： H01L29/78 ,  H01L21/28176 ,  H01L21/324

摘要： An embodiment generally relates a method of processing semiconductor devices. The method includes forming a semiconductor device and exposing the semiconductor device to a temperature substantially between 1175 to 1375 degrees Celsius after the formation of a gate dielectric layer. The method also includes annealing the semiconductor device for a period of time.

摘要翻译： 实施例通常涉及半导体器件的处理方法。 该方法包括形成半导体器件，并且在形成栅极电介质层之后将半导体器件暴露于基本上在1175至1375摄氏度之间的温度。 该方法还包括半导体器件退火一段时间。

公开(公告)号：US07479668B2

公开(公告)日：2009-01-20

申请号：US11370339

申请日：2006-03-08

申请人： Amitabh Jain ,  Gordon Pollack

发明人： Amitabh Jain ,  Gordon Pollack

IPC分类号： H01L31/112

CPC分类号： H01L21/26586 ,  H01L21/324 ,  H01L21/823814 ,  H01L29/6659 ,  H01L29/7833

摘要： The present invention provides, in one embodiment, a process for fabricating a metal oxide semiconductor (MOS) device (100). The process includes forming a gate (120) on a substrate (105) and forming a source/drain extension (160) in the substrate (105). Forming the source/drain extension (160) comprises an abnormal-angled dopant implantation (135) and a dopant implantation (145). The abnormal-angled dopant implantation (135) uses a first acceleration energy and tilt angle of greater than about zero degrees. The dopant implantation (145) uses a second acceleration energy that is higher than the first acceleration energy. The process also includes performing an ultrahigh high temperature anneal of the substrate (105), wherein a portion (170) of the source/drain extension (160) is under the gate (120).

摘要翻译： 本发明在一个实施例中提供一种用于制造金属氧化物半导体（MOS）器件（100）的工艺。 该方法包括在衬底（105）上形成栅极（120）并在衬底（105）中形成源极/漏极延伸部分（160）。 形成源极/漏极延伸部分（160）包括异常倾斜的掺杂剂注入（135）和掺杂剂注入（145）。 异常倾斜的掺杂剂注入（135）使用大于约零度的第一加速能量和倾斜角。 掺杂剂注入（145）使用高于第一加速能量的第二加速能量。 该工艺还包括执行衬底（105）的超高温退火，其中源极/漏极延伸部（160）的部分（170）在栅极（120）下方。