公开(公告)号：US07136441B2

公开(公告)日：2006-11-14

申请号：US10038613

申请日：2002-01-08

申请人： Toru Iwata ,  Hiroyuki Yamauchi ,  Takefumi Yoshikawa

发明人： Toru Iwata ,  Hiroyuki Yamauchi ,  Takefumi Yoshikawa

IPC分类号： H04L7/00

CPC分类号： H04L25/45 ,  H03L7/0807 ,  H03L7/081 ,  H03L7/087 ,  H03L7/0891 ,  H04L7/033

摘要： A driver and a receiver supply a data signal, which is based on serial data having a regular bit pattern, such as a clock, which includes 1's and 0's alternating with each other during an adjustment period, and is based on serial data having an arbitrary bit pattern during a transfer period following the adjustment period. A duty factor controller adjusts a data transition characteristic of the driver or the receiver so that a duty factor of the data signal supplied from the receiver is equal to 50% in the adjustment period, and has the adjusted data transition characteristic stored. A clock recovery unit recovers a clock synchronized with a data signal, which is supplied from the receiver in the transfer period and is based on the adjusted transition characteristic, from the data signal.

公开(公告)号：US20060061395A1

公开(公告)日：2006-03-23

申请号：US10542727

申请日：2003-01-20

申请人： Takayuki Noto ,  Tomoru Sato ,  Hiroyuki Yamauchi

发明人： Takayuki Noto ,  Tomoru Sato ,  Hiroyuki Yamauchi

IPC分类号： H03B1/00

CPC分类号： H04L25/0278 ,  H03K5/086 ,  H03K17/08142 ,  H03K17/164 ,  H03K17/167 ,  H03K19/0005 ,  H04L25/0292

摘要： A semiconductor integrated circuit includes an input circuit for taking in signals and an output circuit for outputting signals. The input circuit is so set that the input impedance during input signal transition is lower than the input impedance on other occasions than input signal transition. The output circuit is so set that the driving force during the second half of signal transition is lower than the driving force during the first half of transition. Such setting that the input impedance during input signal transition is lower than the input impedance on other occasions than input signal transition reduces reflected waves during input signal transition. Such setting that the driving force during the second half of signal transition is lower than the driving force during the first half of transition suppresses production of reflected waves during the second half of signal transition. Thus, the necessity for external components, such as damping resistors and terminator resistors, for impedance matching is obviated.

摘要翻译： 半导体集成电路包括用于接收信号的输入电路和用于输出信号的输出电路。 输入电路设置为输入信号转换期间的输入阻抗低于输入信号转换时的输入阻抗。 输出电路被设定为使得信号转换的后半段的驱动力低于转换前半部分的驱动力。 在输入信号转换期间，输入信号转换期间的输入阻抗比其他情况下的输入阻抗低于输入信号转换的设置会降低输入信号转换期间的反射波。 在信号转换的后半期间的驱动力比转换的前半部分的驱动力低的设定在信号转换的后半期间抑制了反射波的产生。 因此，消除了用于阻抗匹配的诸如阻尼电阻器和终端电阻器的外部组件的必要性。

公开(公告)号：US07012447B2

公开(公告)日：2006-03-14

申请号：US10708238

申请日：2004-02-18

申请人： Hiroyuki Yamauchi ,  Tadahiro Yoshida

发明人： Hiroyuki Yamauchi ,  Tadahiro Yoshida

IPC分类号： H03K19/003

CPC分类号： H01P5/02

摘要： A signal transmitting/receiving apparatus according to the present invention includes: a transmitting device for transmitting data; a receiving device for receiving the data; a data line for transmitting the data; and a supply line for transmitting a bias voltage for determining a voltage of the data line, wherein the transmitting device and the receiving device are connected to each other through the data line and the supply line, the transmitting device including: a driver circuit for outputting the data to the data line; and a bias generating means for generating the bias voltage and outputting the bias voltage to the supply line, the receiving device including: a terminating resistor connected to the data line; and a receiver circuit for detecting the data from the data line, wherein the data line is connected to the supply line via the terminating resistor.

公开(公告)号：US20050264422A1

公开(公告)日：2005-12-01

申请号：US11000206

申请日：2004-12-01

申请人： Toshio Watanabe ,  Hiroyuki Yamauchi

发明人： Toshio Watanabe ,  Hiroyuki Yamauchi

IPC分类号： B65G57/00 ,  G06K7/08 ,  G06K7/10 ,  G06K17/00 ,  G08B13/14 ,  H04B1/59 ,  H04B5/02

CPC分类号： G06K19/07771 ,  G06K7/10178 ,  G06K7/10336

摘要： An IC tag communication relay device is provided with an antenna section, lead lines and input/output unit. The antenna section is equipped with one or more antennas for transmitting and receiving electromagnetic radiation to and from IC tags. The lead lines are connected to each antenna for transmitting electrical signals corresponding to transmitted and received electromagnetic radiation. The input/output unit is arranged outside of the antenna corresponding to each antenna connected to the lead lines.

摘要翻译： IC标签通信中继装置设置有天线部分，引线和输入/输出单元。 天线部分配备有一个或多个天线，用于向IC标签发送和接收电磁辐射。 导线连接到每个天线，用于发送对应于发射和接收的电磁辐射的电信号。 输入/输出单元布置在与连接到引线的每个天线对应的天线的外部。

公开(公告)号：US20050254280A1

公开(公告)日：2005-11-17

申请号：US11121135

申请日：2005-05-04

申请人： Hiroyuki Yamauchi

发明人： Hiroyuki Yamauchi

IPC分类号： G11C17/12 ,  G11C17/00 ,  H01L21/8246 ,  H01L27/112

CPC分类号： G11C17/12 ,  H01L27/112

摘要： A mask ROM includes bit lines, word lines intersecting with the bit lines and bit cells provided along the word lines, each of the bit lines being formed of a cell transistor having a gate connected to an associated one of the word lines. In the mask ROM, further provided is a source node commonly connected to respective sources of ones of the cell transistors having a gate connected to one of adjacent two word lines. A current flows from a selected bit line to a non-selected bit line via a cell transistor selected in reading out data and the source node.

摘要翻译： 掩模ROM包括位线，与位线相交的字线和沿着字线提供的位单元，每个位线由具有连接到相关联的字线之一的栅极的单元晶体管形成。 在掩模ROM中，进一步提供了一个源节点，其通常连接到具有连接到相邻两个字线中的一个的栅极的一个单元晶体管的各个源极。 A电流通过在读出数据和源节点中选择的单元晶体管从选定的位线流向未选择的位线。

公开(公告)号：US20050219921A1

公开(公告)日：2005-10-06

申请号：US11097359

申请日：2005-04-04

申请人： Hiroyuki Yamauchi

发明人： Hiroyuki Yamauchi

IPC分类号： G11C11/413 ,  G11C5/14 ,  G11C7/00 ,  G11C8/08 ,  G11C16/06

CPC分类号： G11C5/145 ,  G11C8/08

摘要： A semiconductor system includes a plurality of memory systems (SARM, ROM, etc.) and circuit systems. The semiconductor system further includes an analog power supply circuit which is common to the memory systems. The analog power supply circuit supplies a source potential to word line drivers of the memory systems. The source potential is set to a potential different from a ground potential and a supply voltage of the semiconductor system.

摘要翻译： 半导体系统包括多个存储器系统（SARM，ROM等）和电路系统。 半导体系统还包括对于存储器系统是共同的模拟电源电路。 模拟电源电路为存储器系统的字线驱动器提供源极电位。 源极电位被设定为与半导体系统的接地电位和电源电压不同的电位。

公开(公告)号：US20050174870A1

公开(公告)日：2005-08-11

申请号：US11101467

申请日：2005-04-08

申请人： Hiroyuki Yamauchi

发明人： Hiroyuki Yamauchi

IPC分类号： G11C7/00 ,  G11C11/00 ,  G11C11/40 ,  G11C11/407 ,  H01L21/8244 ,  H01L27/11

CPC分类号： H01L27/1104

摘要： In a CMOS type SRAM device having a 6-transistor configuration, only a drive transistor and an access transistor of one unit circuit are designed with a larger size, with the other four transistors having a smaller size.

公开(公告)号：USRE38647E1

公开(公告)日：2004-11-09

申请号：US09945603

申请日：2001-09-04

申请人： Hiroyuki Yamauchi ,  Toshio Yamada

发明人： Hiroyuki Yamauchi ,  Toshio Yamada

IPC分类号： G01R1900

CPC分类号： G11C7/065 ,  H03K17/102 ,  H03K17/145

摘要： In order to enhance the sensitivity of a sense amplifier circuit, each one of the transistor pair composing the sense amplifier circuit is formed by transistors connected parallel in an even number of stages, and therefore the sense amplifier circuit is made of transistor pair having an extremely balanced characteristic, cancelling the asymmetricity of current-voltage characteristic of the transistor pair to null.

公开(公告)号：US06728148B2

公开(公告)日：2004-04-27

申请号：US10232785

申请日：2002-08-28

申请人： Hiroyuki Yamauchi

发明人： Hiroyuki Yamauchi

IPC分类号： G11C700

CPC分类号： G11C17/143 ,  G11C17/14 ,  G11C17/18

摘要： A programmed value determining circuit is provided in which both the area of the programmable element and the leak current are reduced. During the first period after power is turned on, both the PMOS transistor Qp1 and the NMOS transistor Qn1 are turned off, and the storage node is disconnected from the power line VDD and the ground line VSS. During the second period after the first period, at least the NMOS transistor Qn1 is turned on, the storage node is connected to the ground line VSS via the program element 10, and the state of the storage node is detected by the detecting portion 11. During the third period after the second period, the PMOS transistor Qp1 and the NMOS transistor Qn1 are turned off, and the state of the storage node is held by the latch portion 12.

摘要翻译： 提供了编程值确定电路，其中可编程元件的面积和漏电流均减小。 在电源接通之后的第一时段期间，PMOS晶体管Qp1和NMOS晶体管Qn1都截止，并且存储节点与电源线VDD和接地线VSS断开。 在第一时段之后的第二周期期间，至少NMOS晶体管Qn1导通，存储节点经由编程元件10连接到接地线VSS，并且由检测部分11检测存储节点的状态。 在第二周期之后的第三周期期间，PMOS晶体管Qp1和NMOS晶体管Qn1截止，存储节点的状态由锁存部12保持。

公开(公告)号：US06633607B1

公开(公告)日：2003-10-14

申请号：US09249695

申请日：1999-02-12

申请人： Hironori Akamatsu ,  Toru Iwata ,  Hiroyuki Yamauchi

发明人： Hironori Akamatsu ,  Toru Iwata ,  Hiroyuki Yamauchi

IPC分类号： H03K904

CPC分类号： H03M9/00 ,  H04L25/49

摘要： A semiconductor device includes: a transmitting section; and a receiving section, wherein the transmitting section and the receiving section are connected to each other through a bus, the transmitting section includes an encoding section for encoding data including a plurality of bits to produce bit-position information which indicates a position of at least one bit selected from the plurality of bits included in the data, and an output section for outputting the bit-position information onto the bus, and the receiving section includes an input section for receiving the bit-position information from the bus, and a decoding section for decoding the bit-position information to produce the data.

摘要翻译： 一种半导体器件包括：发送部分; 以及接收部分，其中所述发送部分和所述接收部分通过总线相互连接，所述发送部分包括用于对包括多个比特的数据进行编码的编码部分，以产生指示至少的位置的比特位置信息 从包含在数据中的多个比特中选择一个比特，以及用于将比特位置信息输出到总线上的输出部分，并且接收部分包括用于从总线接收比特位置信息的输入部分和解码 用于解码位位置信息以产生数据。