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公开(公告)号：US08086934B2
公开(公告)日：2011-12-27
申请号：US11912481
申请日：2006-04-20
IPC分类号： H03M13/00
CPC分类号： H03M13/1168 , H03M13/1114 , H03M13/1137 , H03M13/116 , H03M13/6505 , H03M13/6566
摘要： A decoding apparatus and method are capable of decoding LDPC codes with a high degree of precision while preventing the circuit scale of the decoding apparatus from increasing. A computation section carries out a first computation process corresponding to three check-node processes by making use of decoding intermediate results supplied from a decoding intermediate result storage memory by way of a cyclic shift circuit, and stores the result of the first computation process in a decoding intermediate result storage memory. A computation section carries out a second computation process corresponding to six variable-node processes by making use of decoding intermediate results supplied from a decoding intermediate result storage memory by way of a cyclic shift circuit, and stores the decoding intermediate result in the decoding intermediate result storage memory.
摘要翻译： 解码装置和方法能够以高精度解码LDPC码，同时防止解码装置的电路规模增加。 计算部通过循环移位电路利用从解码中间结果存储存储器提供的解码中间结果，对与三个校验节点处理相对应的第一计算处理进行处理，并将第一计算处理的结果存储在 解码中间结果存储存储器。 计算部通过循环移位电路利用从解码中间结果存储存储器提供的解码中间结果，对与六个可变节点处理相对应的第二计算处理进行解码，并将解码中间结果存储在解码中间结果 存储内存
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52.发明申请INFORMATION PROCESSOR AND INFORMATION PROCESSING METHOD, DISPLAY DEVICE, AND PROGRAM 有权信息处理器和信息处理方法，显示设备和程序公开(公告)号：US20100080329A1
公开(公告)日：2010-04-01
申请号：US12567837
申请日：2009-09-28
IPC分类号： H04B1/10
CPC分类号： H04L25/0212 , H04L25/022 , H04L25/0232 , H04L27/2647 , H04L27/2665
摘要： Disclosed herein is an information processor, including: a receiving section configured to receive an OFDM signal transmitted in accordance with an OFDM system; a FFT arithmetically operating section configured to carry out FFT for a signal within a predetermined interval of the OFDM signal; a delay profile estimating section configured to estimate delay profiles from the OFDM signal received by the receiving section; an inter-symbol interference amount estimating section configured to estimate inter-symbol interference amounts for a plurality of candidates for the predetermined interval, respectively, by using the delay profiles estimated by the delay profile estimating section; and a searching section configured to search for the candidate having the minimum inter-symbol interference amount estimated by the inter-symbol interference amount estimating section from among the plurality of candidates in the predetermined interval, and supply data on the candidate thus searched for as the predetermined interval to the FFT arithmetically operating section.
摘要翻译： 本文公开了一种信息处理器，包括：接收部分，被配置为接收根据OFDM系统传输的OFDM信号; FFT算术运算部，被配置为对所述OFDM信号的预定间隔内的信号进行FFT; 延迟分布估计部，被配置为从所述接收部接收到的OFDM信号估计延迟分布; 符号间干扰量估计部，被配置为通过使用由所述延迟分布估计部估计出的延迟分布，分别估计所述预定间隔的多个候选的符号间干扰量; 以及搜索部，被配置为从所述预定间隔中的所述多个候选中搜索具有由所述符号间干扰量估计部估计的最小符号间干扰量的候选，并且将所搜索的候选者的数据提供为 到FFT运算部分的预定间隔。
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公开(公告)号：US20090221254A1
公开(公告)日：2009-09-03
申请号：US12393093
申请日：2009-02-26
申请人： Hidetoshi Kawauchi , Tadaaki Yuba , Toshiyuki Miyauchi , Takashi Yokokawa , Takuya Okamoto , Tamotsu Ikeda , Koji Naniwada , Kazuhiro Shimizu , Lachlan Bruce Michael
发明人： Hidetoshi Kawauchi , Tadaaki Yuba , Toshiyuki Miyauchi , Takashi Yokokawa , Takuya Okamoto , Tamotsu Ikeda , Koji Naniwada , Kazuhiro Shimizu , Lachlan Bruce Michael
IPC分类号： H04B1/10
CPC分类号： H04B1/1036 , H04L5/0048 , H04L25/0216 , H04L25/0232
摘要： A reception apparatus including an extraction section; a transmission line characteristic estimation section; an interpolation section; a compensation section; a detection section; and a selection section.
摘要翻译： 一种接收装置，包括提取部分; 传输线特性估计部; 插值部分; 赔偿部分; 检测部; 和选择部分。
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公开(公告)号：US07484159B2
公开(公告)日：2009-01-27
申请号：US11071096
申请日：2005-03-03
IPC分类号： H03M13/00
CPC分类号： H03M13/1194 , H03M13/116 , H03M13/118 , H03M13/1185
摘要： Disclosed is an apparatus for encoding data into linear codes on a ring R, including: as many shift registers as the length of information input thereto, the shift registers having a plurality of memory elements; a shift adding unit for adding values which are cyclically input depending on a check matrix for the linear codes, from the shift registers; a storage unit for storing parity values of the linear codes; and an accumulative adding unit for adding a sum from the shift adding unit and the parity values of the linear codes stored in the storage unit to each other to determine new parity values of the linear codes, and supplying the new parity values to the storage unit.
摘要翻译： 公开了一种用于将数据编码成环R上的线性码的装置，包括：与输入的信息的长度一样多的移位寄存器，移位寄存器具有多个存储元件; 移位加法单元，用于根据所述线性代码的校验矩阵从所述移位寄存器中添加循环输入的值; 用于存储线性码的奇偶校验值的存储单元; 以及累积添加单元，用于将存储在存储单元中的从移位加法单元和线性代码的奇偶校验值相加而得到的线性码的新奇偶校验值相加，并将新奇偶校验值提供给存储单元 。
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55.发明授权Decoding device and method, program recording medium, and program using modulation code encoded in accordance with a variable length table 失效解码装置和方法，程序记录介质和使用根据可变长度表编码的调制码的程序公开(公告)号：US07388525B2
公开(公告)日：2008-06-17
申请号：US10532858
申请日：2004-07-05
IPC分类号： H03M7/40
CPC分类号： G11B20/1426 , G11B20/10009 , G11B20/18 , G11B2020/1453 , H03M13/2957 , H03M13/3905 , H03M13/41 , H03M13/6343
摘要： The present invention relates to a decoding apparatus and method, a program storage medium, and a program, which allow high-performance decoding of a modulation code encoded in accordance with a variable-length table. A 17PP-SISO decoder 181 performs SISO decoding on a signal supplied from a PR-SISO decoder 81 by using a Viterbi decoding algorithm or a BCJR decoding algorithm in accordance with a trellis represented by paths corresponding, in a one-to-one fashion, to overall transitions in an entire encoding process in accordance with an encoding table 201 of a 17PP code. A resultant SISO-decoded signal is supplied to a turbo decoder 84 via a deinterleaver 83. The turbo decoder 84 performs turbo decoding on the signal output from the 17PP-SISO decoder 181. The present invention can be applied to a recording/reproducing apparatus for recording/reproducing a signal on/from a storage medium such as a high-density optical disk.
摘要翻译： 本发明涉及一种解码装置和方法，程序存储介质和程序，其允许根据可变长度表编码的调制码的高性能解码。 17PP-SISO解码器181通过使用维特比解码算法或BCJR解码算法对由PR-SISO解码器81提供的信号执行SISO解码，所述维特比解码算法或BCJR解码算法根据以一对一的方式对应的路径表示， 涉及根据17PP码的编码表201的整个编码处理中的整体转换。 经解交织器83将结果SISO解码信号提供给turbo解码器84。 turbo解码器84对从17PP-SISO解码器181输出的信号进行turbo解码。 本发明可以应用于用于在诸如高密度光盘的存储介质上记录/再现信号的记录/再现装置。
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公开(公告)号：US20060192691A1
公开(公告)日：2006-08-31
申请号：US11354000
申请日：2006-02-15
IPC分类号： H03M7/00
CPC分类号： H03M13/458 , H03M13/1191 , H03M13/132 , H03M13/15 , H03M13/1515 , H03M13/152
摘要： The present invention provides a decoding apparatus for carrying out a decoding process on a ring-R linear code. The decoding apparatus includes coded-word holding means for acquiring a coded word with a code length reduced by omission of some symbols from the coded word and for holding the coded word; known-information addition means for attaching a reliability level of each of the symbols omitted from the coded word to reduce its code length as known symbols each having a known value to the coded word held by the coded-word holding means as known information; and repetitive decoding means for repeatedly carrying out a decoding process using belief propagation on the coded word including the known information attached to the coded word by the known-information addition means.
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公开(公告)号：US20050204261A1
公开(公告)日：2005-09-15
申请号：US11071096
申请日：2005-03-03
CPC分类号： H03M13/1194 , H03M13/116 , H03M13/118 , H03M13/1185
摘要： Disclosed is an apparatus for encoding data into linear codes on a ring R, including: as many shift registers as the length of information input thereto, the shift registers having a plurality of memory elements; a shift adding unit for adding values which are cyclically input depending on a check matrix for the linear codes, from the shift registers; a storage unit for storing parity values of the linear codes; and an accumulative adding unit for adding a sum from the shift adding unit and the parity values of the linear codes stored in the storage unit to each other to determine new parity values of the linear codes, and supplying the new parity values to the storage unit.
摘要翻译： 公开了一种用于将数据编码成环R上的线性码的装置，包括：与输入的信息的长度一样多的移位寄存器，移位寄存器具有多个存储元件; 移位加法单元，用于根据所述线性代码的校验矩阵从所述移位寄存器中添加循环输入的值; 用于存储线性码的奇偶校验值的存储单元; 以及累积添加单元，用于将存储在存储单元中的从移位加法单元和线性代码的奇偶校验值相加而得到的线性码的新奇偶校验值相加，并将新奇偶校验值提供给存储单元 。
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公开(公告)号：US4020718A
公开(公告)日：1977-05-03
申请号：US553324
申请日：1975-02-26
申请人： Toshiyuki Miyauchi , Kunio Ohtsuka
发明人： Toshiyuki Miyauchi , Kunio Ohtsuka
CPC分类号： F16H61/0267 , F16H2061/026 , F16H59/20 , F16H59/22 , F16H61/20 , Y10T477/681 , Y10T477/693637
摘要： A hydraulic system for an automatic power transmission of a motor vehicle and adapted for preventing creep of the motor vehicle when the vehicle comes to a complete halt. The hydraulic system includes a first shift valve responsive to throttle pressure and governor pressure to control supply of line pressure into servo means for actuating a friction element to provide lower gear reduction ratio, and a second shift valve responsive to released condition of an accelerator pedal of the vehicle for supplying line pressure into a governor pressure port of the first shift valve, whereby the first shift valve is moved in dependence on throttle pressure and line pressure into a position to supply line pressure into the servo means for thereby effecting shift into the lower gear reduction ratio in the power transmission. The hydraulic system may further include a third shift valve responsive to fully depressed condition of the accelerator pedal to supply line pressure into the first shift valve to apply line pressure thereto so that the shifting point is raised to a higher vehicle speed side during kickdown condition.
摘要翻译： 一种用于机动车辆的自动动力传递的液压系统，适用于当车辆完全停止时防止机动车辆的蠕变。 液压系统包括响应于节气门压力和调速器压力的第一换档阀，以控制线压力的供给到用于致动摩擦元件以提供较低齿轮减速比的伺服装置，以及响应于油门踏板的释放状态的第二换档阀 用于将管路压力供应到第一换挡阀的调速器压力端口的车辆，由此第一换档阀根据节气门压力和管路压力移动到将伺服装置中的管路压力供给到位的位置，从而进入下部 齿轮减速比在动力传动。 液压系统还可以包括第三换档阀，其响应于加速器踏板的完全下压状态，以将管路压力供应到第一换档阀中以将线压力施加到其上，使得换档点在升档状态期间升高到较高车速侧。
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59.发明授权公开(公告)号：US08464124B2
公开(公告)日：2013-06-11
申请号：US12783291
申请日：2010-05-19
IPC分类号： H03M13/00
CPC分类号： H03M13/1128 , H03M13/1105 , H03M13/3715 , H03M13/6552 , H04L1/0053 , H04L1/0057
摘要： A receiving apparatus receives a low density parity check (“LCPC”) code and decode the LCPC code to provide for error check capabilities. A bit error rate (“BER”) controlling section is the frequency of the LCPC by using an index comprised of BER conditional information that indicates communication conditions affecting the power consumption at the time of decoding. The frequency is controlled on the basis of a reception interval of the low density parity check code.
摘要翻译： 接收装置接收低密度奇偶校验（“LCPC”）码并解码LCPC码以提供错误检查能力。 差错率（“BER”）控制部分是通过使用由BER条件信息组成的索引来指示LCPC的频率，该条件信息指示在解码时影响功耗的通信条件。 基于低密度奇偶校验码的接收间隔来控制频率。
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60.发明授权Information processor and information processing method, display device, and program 有权信息处理器和信息处理方法，显示设备和程序公开(公告)号：US08451966B2
公开(公告)日：2013-05-28
申请号：US12567837
申请日：2009-09-28
CPC分类号： H04L25/0212 , H04L25/022 , H04L25/0232 , H04L27/2647 , H04L27/2665
摘要： Disclosed herein is an information processor, including: a receiving section configured to receive an OFDM signal transmitted in accordance with an OFDM system; a FFT arithmetically operating section configured to carry out FFT for a signal within a predetermined interval of the OFDM signal; a delay profile estimating section configured to estimate delay profiles from the OFDM signal received by the receiving section; an inter-symbol interference amount estimating section configured to estimate inter-symbol interference amounts for a plurality of candidates for the predetermined interval, respectively, by using the delay profiles estimated by the delay profile estimating section; and a searching section configured to search for the candidate having the minimum inter-symbol interference amount estimated by the inter-symbol interference amount estimating section from among the plurality of candidates in the predetermined interval, and supply data on the candidate thus searched for as the predetermined interval to the FFT arithmetically operating section.
摘要翻译： 本文公开了一种信息处理器，包括：接收部分，被配置为接收根据OFDM系统传输的OFDM信号; FFT算术运算部，被配置为对所述OFDM信号的预定间隔内的信号进行FFT; 延迟分布估计部，被配置为从所述接收部接收到的OFDM信号估计延迟分布; 符号间干扰量估计部，被配置为通过使用由所述延迟分布估计部估计出的延迟分布，分别估计所述预定间隔的多个候选的符号间干扰量; 以及搜索部，被配置为从所述预定间隔中的所述多个候选中搜索具有由所述符号间干扰量估计部估计的最小符号间干扰量的候选，并且将所搜索的候选者的数据提供为 到FFT运算部分的预定间隔。
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