公开(公告)号：US20060220062A1

公开(公告)日：2006-10-05

申请号：US11100095

申请日：2005-04-05

申请人： Bruce Green ,  Olin Hartin ,  Ellen Lan ,  Philip Li ,  Monte Miller ,  Matthias Passlack ,  Marcus Ray ,  Charles Weitzel

发明人： Bruce Green ,  Olin Hartin ,  Ellen Lan ,  Philip Li ,  Monte Miller ,  Matthias Passlack ,  Marcus Ray ,  Charles Weitzel

IPC分类号： H01L29/739

CPC分类号： H01L29/7785

摘要： In one embodiment, a semiconductor device (500) includes a buffer layer (504) formed over a substrate (502). An AlxGa1-xAs layer (506) is formed over the buffer layer (504) and has a first doped region (508) formed therein. An InxGa1-xAs channel layer (512) is formed over the AlxGa1-xAs layer (506). An AlxGa1-xAs layer (518) is formed over the InxGa1-xAs channel layer (512), and the AlxGa1-xAs layer (518) has a second doped region formed therein. A GaAs layer (520) having a first recess is formed over the AlxGa1-xAs layer (518). A control electrode (526) is formed over the AlxGa1-xAs layer (518). A doped GaAs layer (524) is formed over the undoped GaAs layer (520) and on opposite sides of the control electrode (526) and provides first and second current electrodes. When used to amplify a digital modulation signal, the semiconductor device (500) maintains linear operation over a wide temperature range.

摘要翻译： 在一个实施例中，半导体器件（500）包括形成在衬底（502）上的缓冲层（504）。 在缓冲层（504）之上形成Al x Ga 1-x As层（506），并且在其中形成有第一掺杂区域（508）。 在Al x Ga 1-x 上形成一个In 1 / x Ga 1-x As As沟道层（512） >作为层（506）。 在In 1 x 1 Ga 1-x N上形成Al x Ga 1-x As层（518） 作为沟道层（512）和Al x Ga 1-x As层（518）具有形成在其中的第二掺杂区域。 具有第一凹陷的GaAs层（520）形成在Al 1 Ga 1-x As层（518）上。 控制电极（526）形成在Al 1 Ga 1-x As As层（518）上。 在未掺杂的GaAs层（520）上和控制电极（526）的相对侧上形成掺杂GaAs层（524），并提供第一和第二电流电极。 当用于放大数字调制信号时，半导体器件（500）在宽的温度范围内保持线性操作。

公开(公告)号：US5665658A

公开(公告)日：1997-09-09

申请号：US620688

申请日：1996-03-21

申请人： Matthias Passlack

发明人： Matthias Passlack

IPC分类号： H01L21/316 ,  H01L21/02

CPC分类号： H01L21/31604

摘要： A method of forming a stable semiconductor device on an at least partially completed semiconductor device including a supporting semiconductor structure of III-V material having a clean and atomically ordered surface to be coated with a dielectric layer structure. A relatively thin layer of Ga.sub.2 O.sub.3 is deposited on the surface by evaporation using a high purity single crystal of material including Ga.sub.2 O.sub.3 and a second oxide, such as MgO or Gd.sub.2 O.sub.3. A second layer of material with low bulk trap density relative to the Ga.sub.2 O.sub.3 is deposited on the layer of Ga.sub.2 O.sub.3 to complete the dielectric layer structure.

摘要翻译： 在至少部分完成的半导体器件上形成稳定的半导体器件的方法，该半导体器件包括III-V族材料的支撑半导体结构，该半导体器件具有要涂覆介电层结构的干净且原子序列的表面。 通过使用包括Ga 2 O 3和诸如MgO或Gd 2 O 3的第二氧化物的高纯度单晶的蒸发，在表面上沉积相对薄的Ga 2 O 3层。 相对于Ga 2 O 3具有低体积陷阱密度的第二层材料沉积在Ga 2 O 3层上以完成介电层结构。

公开(公告)号：US5451548A

公开(公告)日：1995-09-19

申请号：US217296

申请日：1994-03-23

申请人： Neil E. J. Hunt ,  Matthias Passlack ,  Erdmann F. Schubert ,  George J. Zydzik

发明人： Neil E. J. Hunt ,  Matthias Passlack ,  Erdmann F. Schubert ,  George J. Zydzik

IPC分类号： C23C14/08 ,  H01L21/203 ,  H01L21/28 ,  H01L21/316 ,  H01L21/441 ,  H01L23/532 ,  H01S5/028 ,  H01L21/00 ,  H01L21/02 ,  H01L21/302 ,  H01L21/463

CPC分类号： C23C14/08 ,  H01L21/02175 ,  H01L21/02269 ,  H01L21/28264 ,  H01L21/31604 ,  H01L21/441 ,  H01L23/5329 ,  H01L2924/0002

摘要： Disclosed is a method of fabricating a stoichiometric gallium oxide (Ga.sub.2 O.sub.3) thin film with dielectric properties on at least a portion of a semiconducting, insulating or metallic substrate. The method comprises electron-beam evaporation of single crystal, high purity Gd.sub.3 Ga.sub.5 O.sub.12 complex compound combining relatively ionic oxide, such as Gd.sub.2 O.sub.3, with the more covalent oxide Ga.sub.2 O.sub.3 such as to deposit a uniform, homogeneous, dense Ga.sub.2 O.sub.3 thin film with dielectric properties on a variety of said substrates, the semiconducting substrates including III-V and II-VI compound semiconductors.

摘要翻译： 公开了一种在半导体，绝缘或金属基底的至少一部分上制造具有介电特性的化学计量的氧化镓（Ga 2 O 3）薄膜的方法。 该方法包括电子束蒸发单晶，高纯Gd3Ga5O12复合化合物，将相对离子氧化物（如Gd2O3）与较多共价氧化物Ga2O3结合，以沉积均匀，均匀致密的Ga2O3薄膜，具有介电性能 的所述衬底，所述半导体衬底包括III-V和II-VI化合物半导体。

公开(公告)号：US08471329B2

公开(公告)日：2013-06-25

申请号：US13298075

申请日：2011-11-16

申请人： Krishna Kumar Bhuwalka ,  Gerben Doornbos ,  Matthias Passlack

发明人： Krishna Kumar Bhuwalka ,  Gerben Doornbos ,  Matthias Passlack

IPC分类号： H01L29/78

CPC分类号： H01L29/7391 ,  H01L29/785

摘要： A tunnel field-effect transistor (TFET) includes a gate electrode, a source region, and a drain region. The source and drain regions are of opposite conductivity types. A channel region is disposed between the source region and the drain region. A source diffusion barrier is disposed between the channel region and the source region. The source diffusion barrier and the source region are under and overlapping the gate electrode. The source diffusion barrier has a first bandgap greater than second bandgaps of the source region, the drain region, and the channel region.

摘要翻译： 隧道场效应晶体管（TFET）包括栅电极，源极区和漏极区。 源区和漏区具有相反的导电类型。 沟道区域设置在源极区域和漏极区域之间。 源极扩散阻挡层设置在沟道区域和源极区域之间。 源极扩散阻挡层和源极区域在栅极电极下方并且重叠。 源极扩散阻挡层具有大于源极区域，漏极区域和沟道区域的第二带隙的第一带隙。

公开(公告)号：US20130134481A1

公开(公告)日：2013-05-30

申请号：US13307738

申请日：2011-11-30

申请人： Krishna Kumar Bhuwalka ,  Gerben Doornbos ,  Matthias Passlack

发明人： Krishna Kumar Bhuwalka ,  Gerben Doornbos ,  Matthias Passlack

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66431 ,  H01L29/1054 ,  H01L29/205 ,  H01L29/267 ,  H01L29/66522 ,  H01L29/66795 ,  H01L29/785

摘要： A Fin Field-Effect Transistor (FinFET) includes a fin, which includes a channel splitter having a first bandgap, and a channel including a first portion and a second portion on opposite sidewalls of the channel splitter. The channel has a second bandgap smaller than the first bandgap. A gate electrode includes a first portion and a second portion on opposite sides of the fin. A gate insulator includes a first portion between the first portion of the gate electrode and the first portion of the channel, and a second portion between the second portion of the gate electrode and the second portion of the channel.

摘要翻译： 鳍场效应晶体管（FinFET）包括鳍，其包括具有第一带隙的沟道分离器和包括在沟道分离器的相对侧壁上的第一部分和第二部分的沟道。 通道具有小于第一带隙的第二带隙。 栅极电极包括在鳍片的相对侧上的第一部分和第二部分。 栅极绝缘体包括位于栅极电极的第一部分和沟道的第一部分之间的第一部分，以及栅电极的第二部分和沟道的第二部分之间的第二部分。

公开(公告)号：US20130119395A1

公开(公告)日：2013-05-16

申请号：US13298075

申请日：2011-11-16

申请人： Krishna Kumar Bhuwalka ,  Gerben Doornbos ,  Matthias Passlack

发明人： Krishna Kumar Bhuwalka ,  Gerben Doornbos ,  Matthias Passlack

IPC分类号： H01L29/78

CPC分类号： H01L29/7391 ,  H01L29/785

摘要： A tunnel field-effect transistor (TFET) includes a gate electrode, a source region, and a drain region. The source and drain regions are of opposite conductivity types. A channel region is disposed between the source region and the drain region. A source diffusion barrier is disposed between the channel region and the source region. The source diffusion barrier and the source region are under and overlapping the gate electrode. The source diffusion barrier has a first bandgap greater than second bandgaps of the source region, the drain region, and the channel region.

摘要翻译： 隧道场效应晶体管（TFET）包括栅电极，源极区和漏极区。 源区和漏区具有相反的导电类型。 沟道区域设置在源极区域和漏极区域之间。 源极扩散阻挡层设置在沟道区域和源极区域之间。 源极扩散阻挡层和源极区域在栅极电极下方并且重叠。 源极扩散阻挡层具有大于源极区域，漏极区域和沟道区域的第二带隙的第一带隙。

公开(公告)号：US07935620B2

公开(公告)日：2011-05-03

申请号：US11950820

申请日：2007-12-05

申请人： Bruce M. Green ,  Haldane S. Henry ,  Chun-Li Liu ,  Karen E. Moore ,  Matthias Passlack

发明人： Bruce M. Green ,  Haldane S. Henry ,  Chun-Li Liu ,  Karen E. Moore ,  Matthias Passlack

IPC分类号： H01L21/28

CPC分类号： H01L21/28581 ,  H01L21/28587 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/432 ,  H01L29/475 ,  H01L29/7787

摘要： Methods and apparatus are described for semiconductor devices. A method comprises providing a partially completed semiconductor device including a substrate, a semiconductor on the substrate, and a passivation layer on the semiconductor, and using a first mask, locally etching the passivation layer to expose a portion of the semiconductor, and without removing the first mask, forming a Schottky contact of a first material on the exposed portion of the semiconductor, then removing the first mask, and using a further mask, forming a step-gate conductor of a second material electrically coupled to the Schottky contact and overlying parts of the passivation layer adjacent to the Schottky contact. By minimizing the process steps between opening the Schottky contact window in the passivation layer and forming the Schottky contact material in this window, the gate leakage of a resulting field effect device having a Schottky gate may be substantially reduced.

摘要翻译： 半导体器件描述了方法和装置。 一种方法包括提供部分完成的半导体器件，其包括衬底，衬底上的半导体和半导体上的钝化层，并且使用第一掩模，局部蚀刻钝化层以暴露半导体的一部分，并且不移除 第一掩模，在半导体的暴露部分上形成第一材料的肖特基接触，然后去除第一掩模，并且使用另外的掩模，形成电耦合到肖特基接触和上覆部分的第二材料的阶梯栅导体 的钝化层与肖特基接触相邻。 通过最小化打开钝化层中的肖特基接触窗口并在该窗口中形成肖特基接触材料之间的工艺步骤，可以显着减少所得到的具有肖特基栅极的场效应器件的栅极泄漏。

公开(公告)号：US07692224B2

公开(公告)日：2010-04-06

申请号：US11864274

申请日：2007-09-28

申请人： Ravindranath Droopad ,  Matthias Passlack

发明人： Ravindranath Droopad ,  Matthias Passlack

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/28264 ,  H01L29/517

摘要： A method of forming a portion (10) of a compound semiconductor MOSFET structure comprises forming a compound semiconductor layer structure (14) and an oxide layer (20) overlying the same. Forming the compound semiconductor structure (14) includes forming at least one channel material (16) and a group-III rich surface termination layer (18) overlying the at least one channel material. Forming the oxide layer (20) includes forming the oxide layer to overlie the group-III rich surface termination layer and comprises one of (a) depositing essentially congruently evaporating oxide of at least one of (a(i)) a ternary oxide and (a(ii)) an oxide more complex than a ternary oxide and (b) depositing oxide molecules, with use of at least one of (b(i)) a ternary oxide and (b(ii)) an oxide more complex than a ternary oxide.

摘要翻译： 形成化合物半导体MOSFET结构的部分（10）的方法包括：形成化合物半导体层结构（14）和覆盖其上的氧化物层（20）。 形成化合物半导体结构（14）包括形成至少一个沟道材料（16）和覆盖至少一个沟道材料的III族富集表面终止层（18）。 形成氧化物层（20）包括形成氧化物层以覆盖III族富集表面终止层，并且包括（a）基本上一致地沉积（a（i））三元氧化物和（ （ii））比三元氧化物更复杂的氧化物和（b）使用（b（i））三元氧化物和（b（ii））中的至少一种沉积氧化物分子，其比 三元氧化物。

公开(公告)号：US20080102607A1

公开(公告)日：2008-05-01

申请号：US11554859

申请日：2006-10-31

申请人： Matthias Passlack ,  Ravindranath Droopad ,  Karthik Rajagopalan

发明人： Matthias Passlack ,  Ravindranath Droopad ,  Karthik Rajagopalan

IPC分类号： H01L21/20

CPC分类号： H01L29/66924 ,  H01L29/2003

摘要： A method of forming a III-V compound semiconductor structure (10) comprises providing a III-V compound semiconductor substrate including a semi-insulating substrate (12) having at least one epitaxial layer formed thereon and further having a gate insulator (14) overlying the at least one epitaxial layer. The at least one epitaxial layer formed on the semi-insulating substrate comprises an epi-structure suitable for use in the formation of a channel of a III-V compound semiconductor MOSFET device, wherein the channel (30) having a first polarity. The method further comprises forming a charge layer (22) at a surface of the gate insulator, the charge layer having a second polarity, wherein the second polarity is opposite to the first polarity.

摘要翻译： 一种形成III-V族化合物半导体结构（10）的方法包括：提供一种III-V族化合物半导体衬底，该III-V族化合物半导体衬底包括半导体衬底（12），该半绝缘衬底具有形成在其上的至少一个外延层，并且还具有覆盖 所述至少一个外延层。 形成在半绝缘衬底上的至少一个外延层包括适于用于形成III-V族化合物半导体MOSFET器件的沟道的外延结构，其中，具有第一极性的沟道（30）。 该方法还包括在栅极绝缘体的表面形成电荷层（22），电荷层具有第二极性，其中第二极性与第一极性相反。

公开(公告)号：US07276456B2

公开(公告)日：2007-10-02

申请号：US11136845

申请日：2005-05-25

申请人： Matthias Passlack ,  Nicholas William Medendorp, Jr.

发明人： Matthias Passlack ,  Nicholas William Medendorp, Jr.

IPC分类号： H01L21/31

CPC分类号： H01L29/513 ,  C23C14/08 ,  C30B23/02 ,  C30B29/16 ,  H01L21/02112 ,  H01L21/02192 ,  H01L21/022 ,  H01L21/02269 ,  H01L21/28194 ,  H01L21/28264 ,  H01L21/31604 ,  H01L21/31666 ,  H01L29/4232 ,  H01L29/511 ,  H01L29/517

摘要： A compound semiconductor structure is provided, which includes a GaAs-based supporting semiconductor structure having a surface on which a dielectric material is to be formed. A first layer of gallium oxide is located on the surface of the supporting semiconductor structure to form an interface therewith. A second layer of a Ga—Gd oxide is disposed on the first layer. The GaAs-based supporting semiconductor structure may be a GaAs-based heterostructure such as an at least partially completed semiconductor device (e.g., a metal-oxide field effect transistor, a heterojunction bipolar transistor, or a semiconductor laser). In this manner a dielectric layer structure is provided which has both a low defect density at the oxide-GaAs interface and a low oxide leakage current density because the dielectric structure is formed from a layer of Ga2O3 followed by a layer of Ga—Gd-oxide. The Ga2O3 layer is used to form a high quality interface with the GaAs-based supporting semiconductor structure while the Ga—Gd-oxide provides a low oxide leakage current density.

摘要翻译： 提供了一种化合物半导体结构，其包括具有其上将要形成介电材料的表面的GaAs基支撑半导体结构。 第一层氧化镓位于支撑半导体结构的表面上以与其形成界面。 在第一层上设置第二层Ga-Gd氧化物。 GaAs基支撑半导体结构可以是诸如至少部分完成的半导体器件（例如，金属氧化物场效应晶体管，异质结双极晶体管或半导体激光器）的基于GaAs的异质结构。 以这种方式，提供了在氧化物 - GaAs界面处具有低缺陷密度和低氧化物漏电流密度的电介质层结构，因为电介质结构由Ga 2 O 2层形成， 然后是一层Ga-Gd氧化物。 Ga 2 O 3层用于与GaAs基支持半导体结构形成高质量的界面，而Ga-Gd氧化物提供低的氧化物漏电流密度 。