公开(公告)号：US10185652B2

公开(公告)日：2019-01-22

申请号：US15606956

申请日：2017-05-26

Applicant: Micron Technology, Inc.

Inventor： Seiji Narui ,  Homare Sato ,  Chikara Kondo

IPC: G11C7/06 ,  G06F12/02 ,  H01L23/522

Abstract: An example apparatus includes a first semiconductor chip and a second semiconductor chip; and a first via and a plurality of second vias coupling the first semiconductor chip and the second semiconductor chip. The first semiconductor chip provides a first timing signal to the first via and further provides first data responsive to the first timing signal to the plurality of second vias. The second semiconductor chip receives the first timing signal from the first via and the first data from the plurality of second vias and further provides the first data responsive to the first timing signal, when the first semiconductor chip is designated, and provides a second timing signal and further provides second data responsive to the second timing signal, when the second semiconductor chip is designated.

公开(公告)号：US20180357156A1

公开(公告)日：2018-12-13

申请号：US16107963

申请日：2018-08-21

Applicant: Micron Technology, Inc.

Inventor： Seiji Narui ,  Homare Sato ,  Chikara Kondo

IPC: G06F12/02 ,  H01L23/522

CPC classification number: G06F12/02 ,  G06F2212/1016 ,  G06F2212/1028 ,  H01L23/5226

Abstract: An example apparatus includes a first semiconductor chip and a second semiconductor chip; and a first via and a plurality of second vias coupling the first semiconductor chip and the second semiconductor chip. The first semiconductor chip provides a first timing signal to the first via and further provides first data responsive to the first timing signal to the plurality of second vias. The second semiconductor chip receives the first timing signal from the first via and the first data from the plurality of second vias and further provides the first data responsive to the first timing signal, when the first semiconductor chip is designated, and provides a second timing signal and further provides second data responsive to the second timing signal, when the second semiconductor chip is designated.

公开(公告)号：US20180293128A1

公开(公告)日：2018-10-11

申请号：US15983073

申请日：2018-05-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Chiaki Dono ,  Seiichi Maruno ,  Taihei Shido ,  Toshio Ninomiya ,  Chikara Kondo

IPC: G06F11/10

CPC classification number: G06F11/1004 ,  G06F11/1016

Abstract: An apparatus includes a first external terminal, a first circuit, a signal line and a second circuit. The first external terminal receives at least one of data mask information and data bus inversion information. The first circuit performs one of an error check operation and a data bus inversion operation. The signal line is coupled between the fist external terminal and the first circuit. The second circuit is coupled to the signal line and first a voltage level of the signal line at a substantially constant level responsive to a first control signal.

公开(公告)号：US20180277175A1

公开(公告)日：2018-09-27

申请号：US15468742

申请日：2017-03-24

Applicant: Micron Technology, Inc.

Inventor： Chikara Kondo ,  Akinori Funahashi

IPC: G11C7/10 ,  G06F13/40 ,  H03M13/29 ,  G11C29/12 ,  G11C29/36

CPC classification number: G06F13/4022 ,  G11C5/063 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/1069 ,  G11C7/1096 ,  G11C29/025 ,  G11C29/12015 ,  G11C29/36 ,  G11C2029/1202 ,  H03M13/29

Abstract: Apparatuses and methods of data communication between semiconductor chips are described. An example apparatus includes: a first die including a first switch circuit that receives a plurality of data signals, and further provides the plurality of data signals to a plurality of corresponding first ports among a plurality of first data ports and a first data redundancy port; and a second die including a second switch circuit that receives the plurality of data signals from the first die at a plurality of corresponding second ports among a plurality of second data ports and a second data redundancy port and further provides the plurality of data signals to a memory array.

公开(公告)号：US09983925B2

公开(公告)日：2018-05-29

申请号：US14678375

申请日：2015-04-03

Applicant: Micron Technology, Inc.

Inventor： Chiaki Dono ,  Seiichi Maruno ,  Taihei Shido ,  Toshio Ninomiya ,  Chikara Kondo

IPC: G11C29/00 ,  G06F11/10

CPC classification number: G06F11/1004 ,  G06F11/1016

Abstract: A control circuit receives the mode signals supplied from a mode register and a read enable signal READ supplied from a control logic circuit, which activates enable signals EN1 to EN3 based on the mode signals and read enable signal. For example, the read enable signal READ is activated when a read command is issued from the controller. One mode signal can indicate an operation mode in which a multi-purpose register is used, and another mode signal can indicate an operation mode in which the data bus inversion function is used. When a data masking operation is disabled and an error check operation is enabled, the mode register activates a protection signal SEL. When the data masking operation is enabled or the error check operation is disabled, the protection signal SEL is deactivated. The operation of a deserializer is controlled by clock signals and the protection signal SEL.

公开(公告)号：US20180096734A1

公开(公告)日：2018-04-05

申请号：US15833425

申请日：2017-12-06

Applicant: Micron Technology, Inc.

Inventor： Chikara Kondo ,  Tomoyuki Shibata ,  Ryota Suzuki

IPC: G11C29/12 ,  G11C29/44 ,  G11C29/56

Abstract: Apparatuses including an interface chip that interfaces with dice through memory channels are described. An example apparatus includes: an interface chip that interfaces with a plurality of dice through a plurality of memory channels, each of the dice comprising a plurality of memory cells, and the interface chip comprising a test circuit. The test circuit includes: first and second terminals corresponding to the first and second memory channels respectively; a test terminal and a built in self test (BIST) circuit common to the first and second memory channels; and a selector coupled to the first and second terminals, the test terminal and the BIST circuit, and couples a first selected one of the first terminal, the test terminal and the BIST circuit to the first channel and a second selected one of the second terminal, the test terminal and the BIST circuit to the second channel.

公开(公告)号：US20170236597A1

公开(公告)日：2017-08-17

申请号：US15045061

申请日：2016-02-16

Applicant: Micron Technology, Inc.

Inventor： Chikara Kondo ,  Tomoyuki Shibata ,  Ryota Suzuki

IPC: G11C29/12

CPC classification number: G11C29/1201 ,  G11C11/417 ,  G11C29/12015 ,  G11C29/4401 ,  G11C29/48 ,  G11C2029/5602

Abstract: Apparatuses including an interface chip that interfaces with dice through memory channels are described. An example apparatus includes: an interface chip that interfaces with a plurality of dice through a plurality of memory channels, each of the dice comprising a plurality of memory cells, and the interface chip comprising a test circuit. The test circuit includes: first and second terminals corresponding to the first and second memory channels respectively; a test terminal and a built in self test (BIST) circuit common to the first and second memory channels; and a selector coupled to the first and second terminals, the test terminal and the BIST circuit, and couples a first selected one of the first terminal, the test terminal and the BIST circuit to the first channel and a second selected one of the second terminal, the test terminal and the BIST circuit to the second channel.