公开(公告)号：US11487610B2

公开(公告)日：2022-11-01

申请号：US15975703

申请日：2018-05-09

Applicant: Micron Technology, Inc.

Inventor： William C. Waldrop ,  Vijayakrishna J. Vankayala ,  Scott E. Smith

IPC: G06F11/00 ,  G06F11/10 ,  G11C29/42

Abstract: Systems and methods are described, in which a parity error alert timing interlock is provided by first waiting for a timer to count a configured parity error pulse width value and then waiting for any in-progress memory operations to complete before deasserting a parity error alert signal that was asserted in response to the detection of a parity error in a command or address.

公开(公告)号：US20220309012A1

公开(公告)日：2022-09-29

申请号：US17807186

申请日：2022-06-16

Applicant: Micron Technology, Inc.

Inventor： Vijayakrishna J. Vankayala

IPC: G06F13/16 ,  G06F11/10 ,  H01L25/065

Abstract: Separate inter-die connectors for data and error correction information and related apparatuses, methods, and computing systems are disclosed. An apparatus including a master die, a target die, inter-die data connectors, and inter-die error correction connectors. The target die includes data storage elements. The inter-die data connectors electrically couple the master die to the target die. The inter-die data connectors are configured to conduct write data bits from the master die to the target die. The write data bits are written to the data storage elements. The inter-die error correction connectors electrically couple the master die to the target die. The inter-die error correction connectors are configured to conduct error correction information corresponding to the write data bits from the master die to the target die. The target die includes error correction circuitry configured to generate new error correction information responsive to the write data bits received from the master die.

公开(公告)号：US11366772B2

公开(公告)日：2022-06-21

申请号：US16819914

申请日：2020-03-16

Applicant: Micron Technology, Inc.

Inventor： Vijayakrishna J. Vankayala

IPC: G06F13/16 ,  G06F11/10 ,  H01L25/065

Abstract: Separate inter-die connectors for data and error correction information and related systems, methods, and devices are disclosed. An apparatus includes a master die, a target die including data storage elements, inter-die data connectors, and inter-die error correction connectors. The inter-die data connectors electrically couple the master die to the target die. The inter-die data connectors are configured to conduct data between the master die and the target die. The inter-die error correction connectors electrically couple the master die to the target die. The inter-die error correction connectors are separate from the inter-die data connectors. The inter-die error correction connectors are configured to conduct error correction information corresponding to the data between the master die and the target die.

公开(公告)号：US20220077112A1

公开(公告)日：2022-03-10

申请号：US17013225

申请日：2020-09-04

Applicant: Micron Technology, Inc

Inventor： Jason M. Brown ,  Vijayakrishna J. Vankayala

IPC: H01L25/065 ,  G11C13/00 ,  G11C29/00

Abstract: A device may include a first die having a first circuit and a second die having a second circuit. The die may be separated by a material layer. The material layer may include multiple through-silicon vias (TSVs) for electrically coupling the first die to the second die. A first TSV of the TSVs may electrically couple the first circuit to the second circuit and a second TSV of the TSVs may include a redundant TSV that electrically bypasses the first TSV to couple the first circuit to the second circuit if a fault is detected in the first TSV.

公开(公告)号：US11127482B1

公开(公告)日：2021-09-21

申请号：US16847181

申请日：2020-04-13

Applicant: Micron Technology, Inc.

Inventor： Bret Addison Johnson ,  Vijayakrishna J. Vankayala

IPC: G11C29/54 ,  G11C29/00 ,  G11C29/12 ,  G11C29/14 ,  G11C29/36 ,  G11C29/04

Abstract: As described, a device may include detection circuitry to detect a deck of a memory array. The deck may include a conductive identifier coupled between a logic high voltage node and the detection circuitry a control circuit coupled to the detection circuit. The control circuit may perform operations including transmitting a test enable signal to the detection circuitry. The detection circuitry may generate a valid signal indicative of an existence of the conductive identifier of the deck in response to the test enable signal. The operations may also include the control circuit receiving the valid signal from the detection circuitry and adjusting a memory operation associated with the memory array based at least in part on the valid signal.

公开(公告)号：US20200342922A1

公开(公告)日：2020-10-29

申请号：US16926505

申请日：2020-07-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Christian N. Mohr ,  Jennifer E. Taylor ,  Vijayakrishna J. Vankayala

IPC: G11C7/10

Abstract: Apparatuses and methods for trimming input buffers based on identified mismatches. An example apparatus includes an input buffer having a first input stage circuit configured to receive a first signal, a second input stage circuit configured to receive a second signal, and an output stage coupled to the first and second input stage circuits and configured to provide an output signal. The first input stage circuit includes serially-coupled transistor pairs that are each coupled between the output stage and a bias voltage. Each of the plurality of serially-coupled transistors pairs are selectively enabled in response to a respective enable signal. The apparatus further including a trim circuit coupled to the first input stage circuit and comprising a plurality of programmable components. The trim circuit is configured to be programmed to provide the respective enable signals based on a detected transition voltage offset relative to a target transition voltage.

公开(公告)号：US20200058344A1

公开(公告)日：2020-02-20

申请号：US16104124

申请日：2018-08-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Vijayakrishna J. Vankayala ,  Jason M. Brown

IPC: G11C11/4076 ,  G11C11/408

Abstract: Apparatuses and methods for a command decoder delay are disclosed. An example apparatus includes a command decoder which may receive memory access command. The command decoder may provide an output command based on the memory access command to a command path at a first time. The command decoder may also provide the output command to a data path at a second time, wherein the second time is delayed relative to the first time.

公开(公告)号：US10395702B1

公开(公告)日：2019-08-27

申请号：US15977125

申请日：2018-05-11

Applicant: Micron Technology, Inc.

Inventor： Jason M. Brown ,  Vijayakrishna J. Vankayala ,  Todd A. Dauenbaugh

IPC: G11C7/22

Abstract: A memory device includes a first data driver configured to send a first data according to a first clock signal; a first data port electrically coupled to the first data driver, the first data port configured to receive the first data; a second data driver configured to send a second data according to a second clock signal, wherein the second clock signal does not match the first clock signal; and a second data port electrically coupled to the second data driver, the second data port configured to receive the second data.

公开(公告)号：US10395701B1

公开(公告)日：2019-08-27

申请号：US15975716

申请日：2018-05-09

Applicant: Micron Technology, Inc.

Inventor： Michael V. Ho ,  Vijayakrishna J. Vankayala

IPC: G11C7/22 ,  G11C11/4063 ,  G11C7/10

Abstract: A memory device includes a timing circuit configured to: receive an input signal, wherein the input signal is one signal within a group of input signals (e.g., multiple bits or nibbles) that are communicated according to a sequence with each of the input signals individually in serial to parallel operations, and generate a grouped latching timing signal based on the received input signal, wherein the timing signal corresponds to nibbles of the data.

公开(公告)号：US10354717B1

公开(公告)日：2019-07-16

申请号：US15976698

申请日：2018-05-10

Applicant: Micron Technology, Inc.

Inventor： Jason M. Brown ,  Vijayakrishna J. Vankayala ,  William C. Waldrop ,  Kallol Mazumder ,  Byung S. Moon ,  Ravi Kiran Kandikonda

IPC: G11C11/4076 ,  G11C11/4093 ,  G06F11/10 ,  G11C11/4096

Abstract: Aspects of the present disclosure eliminating the need for a memory device to have both a shifter that shifts input pin values from an input domain into a parity domain and another shifter that shifts a decoded command from the input domain into the parity domain. A memory device can achieve this by, when parity is being performed, shifting the input from the input pins into the parity domain prior to decoding the command. Using a multiplexer, the decoder can receive the command pin portion of the shifted input when parity checking is being performed and can receive the un-shifted command pin input when parity checking is not being performed. The decoder can use the command pin portion of the shifted input to generate shifted and decoded commands or can use the un-shifted command pin input to generate decoded commands.