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73 条记录 (耗时 0.03 秒)

    High-K metal gate device
    52.
    发明授权
    High-K metal gate device 有权
    高K金属门装置

    公开(公告)号：US08691638B2

    公开(公告)日：2014-04-08

    申请号：US12964748

    申请日：2010-12-10

    申请人： Shyue Seng Tan ,  Chunshan Yin

    发明人： Shyue Seng Tan ,  Chunshan Yin

    IPC分类号： H01L21/00 ,  H01L21/84

    CPC分类号： H01L29/513 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78

    摘要： A method of forming a semiconductor device is presented. The method includes providing a substrate. The method further includes forming a gate stack having a gate electrode on the substrate, which includes forming a metal gate electrode layer. A buffer gate electrode layer is formed on top of the metal gate electrode layer and a top gate electrode layer having a poly-silicon alloy is formed over the metal gate electrode layer.

    摘要翻译： 提出了一种形成半导体器件的方法。 该方法包括提供基板。 该方法还包括在衬底上形成具有栅电极的栅叠层，其包括形成金属栅电极层。 在金属栅极电极层的顶部形成有缓冲栅极电极层，并且在金属栅极电极层上形成具有多晶硅合金的顶部栅极电极层。

    METHOD OF FORMING SOURCE AND DRAIN OF FIELD-EFFECT-TRANSISTOR AND STRUCTURE THEREOF
    57.
    发明申请
    METHOD OF FORMING SOURCE AND DRAIN OF FIELD-EFFECT-TRANSISTOR AND STRUCTURE THEREOF 失效
    形成源和场效应晶体管的方法及其结构

    公开(公告)号：US20080166847A1

    公开(公告)日：2008-07-10

    申请号：US11763561

    申请日：2007-06-15

    申请人： Henry K. Utomo ,  Shailendra Mishra ,  Lee Wee Teo ,  Jae Gon Lee ,  Shyue Seng Tan

    发明人： Henry K. Utomo ,  Shailendra Mishra ,  Lee Wee Teo ,  Jae Gon Lee ,  Shyue Seng Tan

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7843 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7848

    摘要： Embodiments of the invention provide a method of forming a field-effect-transistor (FET). The method includes implanting one or more n-type dopants to create one or more implanted regions with at least a portion of the implanted regions being designated as regions for forming source and drain extensions of the FET; activating the implanted regions; etching with a chlorine based etchant to create openings in the implanted regions, and forming the source and drain extensions by exptaxially growing embedded silicon germanium in the openings. Structure of a semiconductor field-effect-transistor made thereof is also provided.

    摘要翻译： 本发明的实施例提供了形成场效应晶体管（FET）的方法。 该方法包括：注入一个或多个n型掺杂剂以产生一个或多个注入区，其中至少一部分注入区被指定为用于形成FET的源极和漏极扩展的区域; 激活植入区域; 用氯气蚀刻剂蚀刻以在注入区域中形成开口，以及通过在开口中外延生长嵌入式硅锗形成源极和漏极延伸部分。 还提供了由其制成的半导体场效应晶体管的结构。

    Test structure for automatic dynamic negative-bias temperature instability testing
    58.
    发明授权
    Test structure for automatic dynamic negative-bias temperature instability testing 有权
    自动动态负偏置温度不稳定性测试的测试结构

    公开(公告)号：US07103861B2

    公开(公告)日：2006-09-05

    申请号：US10864951

    申请日：2004-06-10

    申请人： Chew Hoe Ang ,  Gang Chen ,  Shyue Seng Tan

    发明人： Chew Hoe Ang ,  Gang Chen ,  Shyue Seng Tan

    IPC分类号： G06F17/50

    CPC分类号： H01L22/34 ,  G01R31/2628 ,  G01R31/2642 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The invention describes a novel test structure and process to create the structure for performing automatic dynamic stress testing of PMOS devices for Negative Bias Temperature Instability (NBTI). The invention consists of an integrated inverter, two integrated electronic switches for switching from stress mode to device DC characterization measurement mode, and a PMOS FET device under test (DUT). The inverter assures the proper 180 degree phase relationship between the test device source and gate voltage while the imbedded electronic switches provide isolation of the test device during DC characterization testing. Another embodiment of the invention enables the testing of multiple devices under test (DUT's).

    摘要翻译： 本发明描述了一种新颖的测试结构和工艺，以创建用于负偏压温度不稳定（NBTI）的PMOS器件的自动动态应力测试的结构。 本发明由集成逆变器，用于从应力模式切换到器件直流表征测量模式的两个集成电子开关以及被测试的PMOS FET器件（DUT）组成。 在DC特性测试期间，嵌入式电子开关提供测试设备的隔离，逆变器确保测试设备源和栅极电压之间正确的180度相位关系。 本发明的另一个实施例能够测试被测试的多个器件（DUT）。

    Control gate
    59.
    发明授权
    Control gate 有权
    控制门

    公开(公告)号：US08647946B2

    公开(公告)日：2014-02-11

    申请号：US12621527

    申请日：2009-11-19

    申请人： Shyue Seng Tan ,  Lee Wee Teo ,  Chunshan Yin

    发明人： Shyue Seng Tan ,  Lee Wee Teo ,  Chunshan Yin

    IPC分类号： H01L21/336

    CPC分类号： H01L29/42364 ,  B82Y10/00 ,  H01L21/26586 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/1045 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

    摘要： A method for forming a semiconductor device is disclosed. The method includes providing a substrate prepared with a second gate structure. An inter-gate dielectric is formed on the substrate and over the second gate. A first gate is also formed. The first gate is adjacent to and separated from the second gate by the inter-gate dielectric. The substrate is patterned to form a split gate structure with the first and second adjacent gates. The split gate structure is provided with an e-field equalizer adjacent to the first gate. The e-field equalizer improves uniformity of e-field across the first gate during operation.

    摘要翻译： 公开了一种用于形成半导体器件的方法。 该方法包括提供用第二栅极结构制备的衬底。 在衬底上并在第二栅极上形成栅极间电介质。 还形成了第一道门。 第一栅极通过栅极间电介质相邻并与第二栅极分离。 图案化衬底以形成具有第一和第二相邻栅极的分离栅极结构。 分离栅极结构设置有与第一栅极相邻的电场均衡器。 电场均衡器在操作期间改善了第一栅极电场的均匀性。

    Method of forming source and drain of field-effect-transistor and structure thereof
    60.
    发明授权
    Method of forming source and drain of field-effect-transistor and structure thereof 失效
    形成场效应晶体管的源极和漏极的方法及其结构

    公开(公告)号：US08138053B2

    公开(公告)日：2012-03-20

    申请号：US11763561

    申请日：2007-06-15

    申请人： Henry K. Utomo ,  Shailendra Mishra ,  Lee Wee Teo ,  Jae Gon Lee ,  Shyue Seng Tan

    发明人： Henry K. Utomo ,  Shailendra Mishra ,  Lee Wee Teo ,  Jae Gon Lee ,  Shyue Seng Tan

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7843 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7848

    摘要： Embodiments of the invention provide a method of forming a field-effect-transistor (FET). The method includes implanting one or more n-type dopants to create one or more implanted regions with at least a portion of the implanted regions being designated as regions for forming source and drain extensions of the FET; activating the implanted regions; etching with a chlorine based etchant to create openings in the implanted regions, and forming the source and drain extensions by exptaxially growing embedded silicon germanium in the openings. Structure of a semiconductor field-effect-transistor made thereof is also provided.

    摘要翻译： 本发明的实施例提供了形成场效应晶体管（FET）的方法。 该方法包括：注入一个或多个n型掺杂剂以产生一个或多个注入区，其中至少一部分注入区被指定为用于形成FET的源极和漏极扩展的区域; 激活植入区域; 用氯气蚀刻剂蚀刻以在注入区域中形成开口，以及通过在开口中外延生长嵌入式硅锗形成源极和漏极延伸部分。 还提供了由其制成的半导体场效应晶体管的结构。