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    Method and apparatus for accessing more than 4 Gigabytes of physical memory with 4-byte table entries
    51.
    发明授权
    Method and apparatus for accessing more than 4 Gigabytes of physical memory with 4-byte table entries 失效
    使用4字节表项访问超过4 GB的物理内存的方法和设备

    公开(公告)号：US06289431B1

    公开(公告)日：2001-09-11

    申请号：US09013414

    申请日：1998-01-26

    申请人： Bryant E. Bigbee ,  Lance E. Hacking ,  Shahrokh Shahidzadeh ,  Shreekant S. Thakkar

    发明人： Bryant E. Bigbee ,  Lance E. Hacking ,  Shahrokh Shahidzadeh ,  Shreekant S. Thakkar

    IPC分类号： G06F1202

    CPC分类号： G06F12/1009

    摘要： A method and apparatus for accessing pages in physical memory, where the physical memory is described. The present invention provides a paged memory system having multiple page sizes. Pages of a first size are accessed via a page directory entry and a corresponding page table entry. The page directory entry stores a base physical address for a corresponding page table and control bits indicating permissions. The page table entry stores a base physical address of the page in memory. In one embodiment, the page table entry inherits permissions from the page directory entry. Pages of a second size are accessed via a page directory entry that stores a base physical address of the page and control bits indicating permissions associated with the page. In another embodiment, entries to the page directory table and the page table are 4-bytes in size and provide paging for memory up to 1.1 Terabytes in size.

    摘要翻译： 一种用于访问物理存储器中的页面的方法和装置，其中描述了物理存储器。 本发明提供了一种具有多页尺寸的分页存储系统。 通过页面目录条目和对应的页面表项访问第一个大小的页面。 页目录条目存储相应页表的基本物理地址和指示许可的控制位。 页表条目将页面的基本物理地址存储在存储器中。 在一个实施例中，页表条目从页目录条目继承权限。 通过存储页面的基本物理地址的页目录条目和指示与页面相关联的权限的控制位来访问第二大小的页面。 在另一个实施例中，到页目录表和页表的条目大小为4字节，并为大小为1.1TB的内存提供寻呼。

    Memory attribute palette
    52.
    发明授权
    Memory attribute palette 失效
    内存属性调色板

    公开(公告)号：US5946713A

    公开(公告)日：1999-08-31

    申请号：US914578

    申请日：1997-08-18

    申请人： Lance E. Hacking ,  Bryant E. Bigbee ,  Shahrokh Shahidzadeh ,  Shreekant S. Thakkar

    发明人： Lance E. Hacking ,  Bryant E. Bigbee ,  Shahrokh Shahidzadeh ,  Shreekant S. Thakkar

    IPC分类号： G06F12/10 ,  G06F12/08 ,  G06F12/02

    CPC分类号： G06F12/0802

    摘要： The present invention relates to a computer system in which linear memory attributes are specified. Physical memory attributes may also be specified in physical attribute registers. A memory attribute palette (MAP) receives index signals and selects linear memory attributes in response to the index signals. An effective memory attribute selector receives selected linear memory attribute signals and, if present, the physical memory attribute signals and, in response thereto, selects effective memory attribute signals to present an effective memory attribute. In a preferred embodiment, the linear memory attributes may be programmably written into one or more registers, thereby allowing a program or OS flexibility in the choice of memory attributes, including memory attributes not currently used. The invention allows a program to apply a memory attribute of choice to a particular section of memory, thereby allowing the computer system to provide higher performance.

    摘要翻译： 本发明涉及一种其中规定了线性存储器属性的计算机系统。 物理存储器属性也可以在物理属性寄存器中指定。 存储器属性调色板（MAP）接收索引信号并响应于索引信号选择线性存储器属性。 有效存储器属性选择器接收所选择的线性存储器属性信号，并且如果存在物理存储器属性信号，并且响应于此，选择有效存储器属性信号以呈现有效存储器属性。 在优选实施例中，线性存储器属性可以可编程地写入一个或多个寄存器，从而允许程序或OS灵活地选择存储器属性，包括当前未使用的存储器属性。 本发明允许程序将选择的存储器属性应用于存储器的特定部分，从而允许计算机系统提供更高的性能。

    Integrating Non-Peripheral Component Interconnect (PCI) Resources Into A Personal Computer System
    55.
    发明申请
    Integrating Non-Peripheral Component Interconnect (PCI) Resources Into A Personal Computer System 有权
    将非外围组件互连（PCI）资源集成到个人计算机系统中

    公开(公告)号：US20120233366A1

    公开(公告)日：2012-09-13

    申请号：US13477631

    申请日：2012-05-22

    申请人： Arvind Mandhani ,  Woojong Han ,  Ken Shoemaker ,  Madhu Athreya ,  Mahesh Wagh ,  Shreekant S. Thakkar

    发明人： Arvind Mandhani ,  Woojong Han ,  Ken Shoemaker ,  Madhu Athreya ,  Mahesh Wagh ,  Shreekant S. Thakkar

    IPC分类号： G06F13/42

    CPC分类号： G06F13/4022 ,  G06F13/4027 ,  G06F13/404 ,  G06F13/4045 ,  G06F13/42

    摘要： In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed.

    摘要翻译： 在一个实施例中，本发明包括具有根据个人计算机（PC）协议和第二协议进行通信的适配器的装置。 耦合到适配器的第一接口是对从适配器的上游接收的事务执行地址转换和排序。 第一个接口依次耦合到异构资源，每个资源包括知识产权（IP）核心和垫片，其中垫片将为IP核实现PC协议的头部，以使其能够并入设备中而无需 修改。 描述和要求保护其他实施例。

    Integrating Non-Peripheral Component Interconnect (PCI) Resources Into A Personal Computer System
    57.
    发明申请
    Integrating Non-Peripheral Component Interconnect (PCI) Resources Into A Personal Computer System 有权
    将非外围组件互连（PCI）资源集成到个人计算机系统中

    公开(公告)号：US20110271021A1

    公开(公告)日：2011-11-03

    申请号：US13180697

    申请日：2011-07-12

    申请人： Arvind Mandhani ,  Woojong Han ,  Ken Shoemaker ,  Madhu Athreya ,  Mahesh Wagh ,  Shreekant S. Thakkar

    发明人： Arvind Mandhani ,  Woojong Han ,  Ken Shoemaker ,  Madhu Athreya ,  Mahesh Wagh ,  Shreekant S. Thakkar

    IPC分类号： G06F13/42

    CPC分类号： G06F13/4022 ,  G06F13/4027 ,  G06F13/404 ,  G06F13/4045 ,  G06F13/42

    摘要： In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed.

    摘要翻译： 在一个实施例中，本发明包括具有根据个人计算机（PC）协议和第二协议进行通信的适配器的装置。 耦合到适配器的第一接口是对从适配器的上游接收的事务执行地址转换和排序。 第一个接口依次耦合到异构资源，每个资源包括知识产权（IP）核心和垫片，其中垫片将为IP核实现PC协议的头部，以使其能够并入设备中而无需 修改。 描述和要求保护其他实施例。

    Method and apparatus for caching memory content on a computing system to facilitate instant-on resuming from a hibernation state
    59.
    发明授权
    Method and apparatus for caching memory content on a computing system to facilitate instant-on resuming from a hibernation state 有权
    用于在计算系统上缓存存储器内容以便于从休眠状态即时恢复的方法和装置

    公开(公告)号：US07594073B2

    公开(公告)日：2009-09-22

    申请号：US11541113

    申请日：2006-09-29

    申请人： Ulf R. Hanebutte ,  Ram Chary ,  Pradeep Sebastian ,  Shubha Kumbadakone ,  Shreekant S. Thakkar

    发明人： Ulf R. Hanebutte ,  Ram Chary ,  Pradeep Sebastian ,  Shubha Kumbadakone ,  Shreekant S. Thakkar

    IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F1/26 ,  G06F1/32 ,  G06G1/00

    CPC分类号： G06F12/0866 ,  Y02D10/13

    摘要： The memory content may be cached in the non-volatile cache when a computing system is entering S4 state. The non-volatile cache may be coupled to a bus that connects the disk drive with the disk controller. When resuming from S4 state, the memory content may be read from the non-volatile cache rather than from the slow disk drive, which facilitates instant-on resuming for the system. The caching process may be performed in an OS-transparent manner. During the caching process, data with contiguous addresses may be merged into a block of data. A mapping table may be created and stored in the non-volatile cache which includes multiple entries, each for a block of data. The mapping table facilitates data reading from the non-volatile cache to provide instant-on resuming from S4 state.

    摘要翻译： 当计算系统进入S4状态时，存储器内容可以被缓存在非易失性高速缓存中。 非易失性缓存可以耦合到将盘驱动器与盘控制器连接的总线。 当从S4状态恢复时，可以从非易失性高速缓存而不是从慢磁盘驱动器读取存储器内容，这有助于系统的即时恢复。 缓存过程可以以OS透明的方式执行。 在缓存过程中，具有连续地址的数据可以被合并到一个数据块中。 可以创建映射表并将其存储在非易失性高速缓存中，其包括多个条目，每个条目用于数据块。 该映射表便于从非易失性高速缓存中进行数据读取，以提供从S4状态的即时恢复。