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    Multi-port magnetic random access memory (MRAM)
    52.
    发明授权
    Multi-port magnetic random access memory (MRAM) 有权
    多端口磁随机存取存储器（MRAM）

    公开(公告)号：US08670264B1

    公开(公告)日：2014-03-11

    申请号：US13585774

    申请日：2012-08-14

    Applicant: Ebrahim Abedifard ,  Parviz Keshtbod

    Inventor： Ebrahim Abedifard ,  Parviz Keshtbod

    IPC: G11C11/21

    CPC classification number: G11C11/1673 ,  G11C8/16 ,  G11C11/16 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1675

    Abstract: A memory array is organized into rows and columns of resistive elements and is disclosed to include a resistive element to be read or to be written thereto. Further, a first access transistor is coupled to the resistive element and to a first source line and a second access transistor is coupled to the resistive element and to a second source line, the resistive element being coupled at one end to the first and second access transistors and at an opposite end to a bit line. The memory array further has other resistive elements that are each coupled to the bit line. The resistive element is written to while one or more of the other resistive elements are being read.

    Abstract translation: 存储器阵列被组织成电阻元件的行和列，并且被公开为包括要读取或要写入的电阻元件。 此外，第一存取晶体管耦合到电阻元件和第一源极线，第二存取晶体管耦合到电阻元件和第二源极线，电阻元件在一端被耦合到第一和第二存取 晶体管和位线的相对端。 存储器阵列还具有各自耦合到位线的其它电阻元件。 在读取其中一个或多个其它电阻元件的同时写入电阻元件。

    Method of sensing data of a magnetic random access memories (MRAM)
    53.
    发明授权
    Method of sensing data of a magnetic random access memories (MRAM) 有权
    用于检测磁随机存取存储器（MRAM）的数据的方法

    公开(公告)号：US08644060B2

    公开(公告)日：2014-02-04

    申请号：US13491159

    申请日：2012-06-07

    Applicant: Ebrahim Abedifard ,  Parviz Keshtbod

    Inventor： Ebrahim Abedifard ,  Parviz Keshtbod

    IPC: G11C11/00

    CPC classification number: G11C11/1673 ,  G11C11/1657

    Abstract: A MTJ is sensed by applying a first reference current, first programming the MTJ to a first value using the first reference current, detecting the resistance of the first programmed MTJ, and if the detected resistance is above a first reference resistance, declaring the MTJ to be at a first state. Otherwise, upon determining if the detected resistance is below a second reference resistance, declaring the MTJ to be at a second state. In some cases, applying a second reference current through the MTJ and second programming the MTJ to a second value using the second reference current. Detecting the resistance of the second programmed MTJ and in some cases, declaring the MTJ to be at the second state, and in other cases, declaring the MTJ to be at the first state and programming the MTJ to the second state.

    Abstract translation: 通过施加第一参考电流来感测MTJ，首先使用第一参考电流将MTJ编程为第一值，检测第一编程MTJ的电阻，并且如果检测到的电阻高于第一参考电阻，则将MTJ声明为 处于第一个状态。 否则，在确定检测到的电阻是否低于第二参考电阻时，声明MTJ处于第二状态。 在某些情况下，通过MTJ施加第二参考电流，并使用第二参考电流对MTJ进行第二次编程。 检测第二个编程的MTJ的电阻，并且在某些情况下，声明MTJ处于第二状态，在其他情况下，声明MTJ处于第一状态并将MTJ编程到第二状态。

    Redeposition Control in MRAM Fabrication Process
    54.
    发明申请
    Redeposition Control in MRAM Fabrication Process 有权

    公开(公告)号：US20130341801A1

    公开(公告)日：2013-12-26

    申请号：US13530381

    申请日：2012-06-22

    Applicant: Kimihiro Satoh ,  Dong Ha Jung ,  Ebrahim Abedifard ,  Parviz Keshtbod ,  Yiming Huai ,  Jing Zhang

    Inventor： Kimihiro Satoh ,  Dong Ha Jung ,  Ebrahim Abedifard ,  Parviz Keshtbod ,  Yiming Huai ,  Jing Zhang

    IPC: H01L23/498 ,  H01L21/768

    CPC classification number: H01L43/02 ,  H01L27/222 ,  H01L43/12

    Abstract: Methods and structures are described to reduce metallic redeposition material in the memory cells, such as MTJ cells, during pillar etching. One embodiment forms metal studs on top of the landing pads in a dielectric layer that otherwise covers the exposed metal surfaces on the wafer. Another embodiment patterns the MTJ and bottom electrode separately. The bottom electrode mask then covers metal under the bottom electrode. Another embodiment divides the pillar etching process into two phases. The first phase etches down to the lower magnetic layer, then the sidewalls of the barrier layer are covered with a dielectric material which is then vertically etched. The second phase of the etching then patterns the remaining layers. Another embodiment uses a hard mask above the top electrode to etch the MTJ pillar until near the end point of the bottom electrode, deposits a dielectric, then vertically etches the remaining bottom electrode.

    Non-uniform switching based non-volatile magnetic based memory
    59.
    发明授权
    Non-uniform switching based non-volatile magnetic based memory 有权
    基于非均匀开关的非易失性磁性存储器

    公开(公告)号：US08389301B2

    公开(公告)日：2013-03-05

    申请号：US13305668

    申请日：2011-11-28

    Applicant: Rajiv Yadav Ranjan ,  Petro Estakhri ,  Mahmud Assar ,  Parviz Keshtbod

    Inventor： Rajiv Yadav Ranjan ,  Petro Estakhri ,  Mahmud Assar ,  Parviz Keshtbod

    IPC: H01L21/00

    CPC classification number: H01L27/228 ,  B82Y10/00 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  H01L43/08

    Abstract: A non-uniform switching based non-volatile magnetic memory element includes a fixed layer, a barrier layer formed on top of the fixed layer, a first free layer formed on top of the barrier layer, a non-uniform switching layer (NSL) formed on top of the first free layer, and a second free layer formed on top of the non-uniform switching layer. Switching current is applied, in a direction that is substantially perpendicular to the fixed layer, barrier layer, first free layer, non-uniform switching layer and the second free layer causing switching between states of the first free layer, second free layer and non-uniform switching layer with substantially reduced switching current.

    Abstract translation: 非均匀开关型非易失性磁存储元件包括固定层，形成在固定层顶部上的阻挡层，形成在阻挡层顶部上的第一自由层，形成非均匀开关层（NSL） 在第一自由层的顶部和形成在不均匀开关层的顶部上的第二自由层。 在基本上垂直于固定层，阻挡层，第一自由层，不均匀的开关层和第二自由层的方向上施加开关电流，导致第一自由层，第二自由层和非自由层的状态之间的切换， 均匀的开关层，开关电流大大降低。

    NON-VOLATILE MAGNETIC MEMORY WITH LOW SWITCHING CURRENT AND HIGH THERMAL STABILITY
    60.
    发明申请
    NON-VOLATILE MAGNETIC MEMORY WITH LOW SWITCHING CURRENT AND HIGH THERMAL STABILITY 有权
    具有低开关电流和高热稳定性的非易失性磁记忆体

    公开(公告)号：US20120205763A1

    公开(公告)日：2012-08-16

    申请号：US13455888

    申请日：2012-04-25

    Applicant: Rajiv Yadav Ranjan ,  Parviz Keshtbod

    Inventor： Rajiv Yadav Ranjan ,  Parviz Keshtbod

    IPC: H01L29/82

    CPC classification number: H01L43/10 ,  B82Y10/00 ,  G11C11/161 ,  G11C11/1675 ,  H01L27/228

    Abstract: A non-volatile current-switching magnetic memory element includes a bottom electrode, a pinning layer formed on top of the bottom electrode, and a fixed layer formed on top of the pinning layer. The memory element further includes a tunnel layer formed on top of the pinning layer, a first free layer formed on top of the tunnel layer, a granular film layer formed on top of the free layer, a second free layer formed on top of the granular film layer, a cap layer formed on top of the second layer and a top electrode formed on top of the cap layer.

    Abstract translation: 非易失性电流切换磁存储元件包括底电极，形成在底电极顶部的钉扎层和形成在钉扎层顶部上的固定层。 存储元件还包括形成在钉扎层顶部的隧道层，形成在隧道层顶部上的第一自由层，形成在自由层顶部上的颗粒膜层，形成在颗粒状的顶部上的第二自由层 膜层，形成在第二层的顶部上的盖层和形成在盖层的顶部上的顶部电极。

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