公开(公告)号：US09158660B2

公开(公告)日：2015-10-13

申请号：US13422546

申请日：2012-03-16

申请人： Mark S. Farrell ,  Charles W. Gainey, Jr. ,  Marcel Mitran ,  Chung-Lung K. Shum ,  Timothy J. Slegel ,  Brian L. Smith ,  Kevin A. Stoodley

发明人： Mark S. Farrell ,  Charles W. Gainey, Jr. ,  Marcel Mitran ,  Chung-Lung K. Shum ,  Timothy J. Slegel ,  Brian L. Smith ,  Kevin A. Stoodley

IPC分类号： G06F11/36

CPC分类号： G06F11/3644 ,  G06F9/30076 ,  G06F9/30101 ,  G06F11/3636 ,  G06F11/3648

摘要： An aspect includes enabling and disabling execution of a run-time instrumentation facility. An instruction for execution by the processor in a lesser privileged state is fetched by the processor. The instruction is executed based on determining, by the processor, that the run-time instrumentation facility permits execution of the instruction in the lesser-privileged state and that controls associated with the run-time instrumentation facility are valid. The run-time instrumentation facility is disabled based on the instruction being a run-time instrumentation facility off (RIOFF) instruction. The disabling includes updating a bit in a program status word (PSW) of the processor to indicate that run-time instrumentation data should not be captured by the processor. The run-time instrumentation facility is enabled based on the instruction being a run-time instrumentation facility on (RION) instruction. The enabling includes updating the bit in the PSW to indicate that run-time instrumentation data should be captured by the processor.

摘要翻译： 一个方面包括启用和禁用运行时仪器设施的执行。 处理器处于较低特权状态的执行指令由处理器提取。 该指令是基于由处理器确定运行时仪表设备允许执行较弱特权状态的指令并且与运行时仪表设备相关联的控制是有效的而执行的。 基于运行时间仪器设备（RIOFF）指令的指令，运行时仪表设备被禁用。 禁用包括更新处理器的程序状态字（PSW）中的位以指示运行时仪表数据不应被处理器捕获。 基于（RION）指令的运行时仪表设备的指令启用运行时仪表设备。 启用包括更新PSW中的位以指示运行时仪表数据应由处理器捕获。

公开(公告)号：US09021493B2

公开(公告)日：2015-04-28

申请号：US13615704

申请日：2012-09-14

申请人： Fadi Y. Busaba ,  Steven R. Carlough ,  Christopher A. Krygowski ,  Brian R. Prasky ,  Chung-Lung K. Shum

发明人： Fadi Y. Busaba ,  Steven R. Carlough ,  Christopher A. Krygowski ,  Brian R. Prasky ,  Chung-Lung K. Shum

IPC分类号： G06F9/46 ,  G06F9/38 ,  G06F9/50

CPC分类号： G06F9/5038 ,  G06F9/38 ,  G06F9/45533 ,  G06F9/4881 ,  G06F9/50 ,  G06F9/5011 ,  G06F9/5016 ,  G06F9/5077 ,  G06F2009/45591 ,  G06F2209/483 ,  G06F2209/5021 ,  G06F2209/504 ,  G06F2209/507 ,  G06F2209/508 ,  Y02B70/30 ,  Y02D10/22

摘要： Resources in a computing environment are managed, for example, by a hardware controller controlling dispatching of resources from one or more pools of resources to be used in execution of threads. The controlling includes conditionally dispatching resources from the pool(s) to one or more low-priority threads of the computing environment based on current usage of resources in the pool(s) relative to an associated resource usage threshold. The management further includes monitoring resource dispatching from the pool(s) to one or more high-priority threads of the computing environment, and based on the monitoring, dynamically adjusting the resource usage threshold used in the conditionally dispatching of resources from the pool(s) to the low-priority thread(s).

公开(公告)号：US08930627B2

公开(公告)日：2015-01-06

申请号：US13523453

申请日：2012-06-14

申请人： Khary J. Alexander ,  Chung-Lung K. Shum

发明人： Khary J. Alexander ,  Chung-Lung K. Shum

IPC分类号： G06F12/08

CPC分类号： G06F12/084 ,  G06F12/08

摘要： A computer program product for mitigating conflicts for shared cache lines between an owning core currently owning a cache line and a requestor core. The computer program product includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes determining whether the owning core is operating in a transactional or non-transactional mode and setting a hardware-based reject threshold at a first or second value with the owning core determined to be operating in the transactional or non-transactional mode, respectively. The method further includes taking first or second actions to encourage cache line sharing between the owning core and the requestor core in response to a number of rejections of requests by the requestor core reaching the reject threshold set at the first or second value, respectively.

摘要翻译： 一种用于减轻当前拥有高速缓存行和请求者核心的所有核心之间的共享高速缓存行的冲突的计算机程序产品。 计算机程序产品包括可由处理电路读取的有形存储介质，并且存储由处理电路执行以执行方法的指令。 该方法包括确定所拥有的核心是以事务性还是非交易模式操作，并且将所确定的拥有核心分别以事务性或非事务性模式操作的第一或第二值设置为基于硬件的拒绝阈值 。 该方法还包括采取第一或第二动作以响应于请求者核心达到以第一或第二值设置的拒绝阈值的请求的拒绝次数来鼓励拥有核心和请求者核心之间的高速缓存行共享。

公开(公告)号：US20140082625A1

公开(公告)日：2014-03-20

申请号：US13615704

申请日：2012-09-14

申请人： Fadi Y. Busaba ,  Steven R. Carlough ,  Christopher A. Krygowski ,  Brian R. Prasky ,  Chung-Lung K. Shum

发明人： Fadi Y. Busaba ,  Steven R. Carlough ,  Christopher A. Krygowski ,  Brian R. Prasky ,  Chung-Lung K. Shum

IPC分类号： G06F9/50

CPC分类号： G06F9/5038 ,  G06F9/38 ,  G06F9/45533 ,  G06F9/4881 ,  G06F9/50 ,  G06F9/5011 ,  G06F9/5016 ,  G06F9/5077 ,  G06F2009/45591 ,  G06F2209/483 ,  G06F2209/5021 ,  G06F2209/504 ,  G06F2209/507 ,  G06F2209/508 ,  Y02B70/30 ,  Y02D10/22

摘要： Resources in a computing environment are managed, for example, by a hardware controller controlling dispatching of resources from one or more pools of resources to be used in execution of threads. The controlling includes conditionally dispatching resources from the pool(s) to one or more low-priority threads of the computing environment based on current usage of resources in the pool(s) relative to an associated resource usage threshold. The management further includes monitoring resource dispatching from the pool(s) to one or more high-priority threads of the computing environment, and based on the monitoring, dynamically adjusting the resource usage threshold used in the conditionally dispatching of resources from the pool(s) to the low-priority thread(s).

摘要翻译： 计算环境中的资源例如通过硬件控制器进行管理，硬件控制器控制从用于执行线程的一个或多个资源池中调度资源。 所述控制包括基于所述池中的资源相对于相关联的资源使用阈值的当前使用情况，将资源从所述池有条件地调度到所述计算环境的一个或多个低优先级线程。 该管理还包括监视从该池到该计算环境的一个或多个高优先级线程的资源调度，并且基于该监视，动态地调整在从池中有条件地分派资源中使用的资源使用阈值 ）到低优先级线程。

公开(公告)号：US08645670B2

公开(公告)日：2014-02-04

申请号：US12031998

申请日：2008-02-15

申请人： Brian D. Barrick ,  Chung-Lung K. Shum ,  Aaron Tsai

发明人： Brian D. Barrick ,  Chung-Lung K. Shum ,  Aaron Tsai

IPC分类号： G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F13/00 ,  G06F13/28

CPC分类号： G06F9/30043 ,  G06F9/3824 ,  G06F9/3826

摘要： A processor including an architecture for limiting store operations includes: a data input and a cache input as inputs to data merge logic; a merge buffer for providing an output to an old data buffer, holding a copy of a memory location and two way communication with a new data buffer; compare logic for receiving old data from the old data buffer and new data from the new data buffer and comparing if the old data matches the new data, and if there is a match determining an existence of a silent store; and store data control logic for limiting store operations while the silent store exists. A method and a computer program product are provided.

摘要翻译： 包括用于限制存储操作的架构的处理器包括：作为数据合并逻辑的输入的数据输入和高速缓存输入; 用于向旧数据缓冲器提供输出的合并缓冲器，保持存储器位置的副本和与新数据缓冲器的双向通信; 比较用于从旧数据缓冲器接收旧数据和来自新数据缓冲器的新数据的比较逻辑，并比较旧数据是否与新数据匹配，以及是否存在确定存在静默存储的匹配; 并存储用于限制存储操作的数据控制逻辑，同时存在无声存储。 提供了一种方法和计算机程序产品。

公开(公告)号：US20140019803A1

公开(公告)日：2014-01-16

申请号：US13548448

申请日：2012-07-13

申请人： Fadi Y. Busaba ,  Steven R. Carlough ,  Christopher A. Krygowski ,  Brian R. Prasky ,  Chung-Lung K. Shum

发明人： Fadi Y. Busaba ,  Steven R. Carlough ,  Christopher A. Krygowski ,  Brian R. Prasky ,  Chung-Lung K. Shum

IPC分类号： G06F11/14

CPC分类号： G06F11/1479 ,  G06F11/1438

摘要： A computer system includes a simultaneous multi-threading processor and memory in operable communication with the processor. The processor is configured to perform a method including running multiple threads simultaneously, detecting a hardware error in one or more hardware structures of the processing circuit, and identifying one or more victim threads of the multiple threads. The processor is further configured to identify a plurality of hardware structures associated with execution of the one or more victim threads, isolate the one or more victim threads from the rest of the multiple threads by preventing access to the plurality of hardware structures by the multiple threads, flush the one or more victim threads by resetting hardware states of the plurality of hardware structures, and restore the one or more victim threads by restoring the plurality of hardware structures to a known safe state.

摘要翻译： 计算机系统包括同时多线程处理器和与处理器可操作地通信的存储器。 处理器被配置为执行包括同时运行多个线程的方法，检测处理电路的一个或多个硬件结构中的硬件错误，以及识别多个线程的一个或多个受害者线程。 所述处理器还被配置为识别与所述一个或多个受害者线程的执行相关联的多个硬件结构，通过所述多个线程阻止对所述多个硬件结构的访问来将所述一个或多个受害者线程与所述多个线程的其余部分隔离 通过重置多个硬件结构的硬件状态来刷新一个或多个受害者线程，并通过将多个硬件结构恢复到已知的安全状态来恢复一个或多个受害者线程。

公开(公告)号：US20130339650A1

公开(公告)日：2013-12-19

申请号：US13523919

申请日：2012-06-15

申请人： Khary J. Alexander ,  Ilia Averbouch ,  Ariel J. Birnbaum ,  Jonathan T. Hsieh ,  Christian Jacobi ,  Shmuel Paycher ,  Chung-Lung K. Shum

发明人： Khary J. Alexander ,  Ilia Averbouch ,  Ariel J. Birnbaum ,  Jonathan T. Hsieh ,  Christian Jacobi ,  Shmuel Paycher ,  Chung-Lung K. Shum

IPC分类号： G06F12/10

CPC分类号： G06F12/0862 ,  G06F12/1009

摘要： Embodiments relate to prefetch address translation in a computer processor. An aspect includes issuing, by prefetch logic, a prefetch request comprising a virtual page address. Another aspect includes, based on the prefetch request missing the TLB and the address translation logic of the processor being busy performing a current translation request, comparing a page of the prefetch request to a page of the current translation request. Yet another aspect includes, based on the page of the prefetch request matching the page of the current translation request, storing the prefetch request in a prefetch buffer.

摘要翻译： 实施例涉及计算机处理器中的预取地址转换。 一方面包括通过预取逻辑发出包括虚拟页面地址的预取请求。 另一方面包括：基于预取请求，丢失TLB，处理器的地址转换逻辑正在执行当前转换请求，将预取请求的页面与当前转换请求的页面进行比较。 另一方面包括：基于与当前转换请求的页面匹配的预取请求的页面，将预取请求存储在预取缓冲器中。

公开(公告)号：US20130339625A1

公开(公告)日：2013-12-19

申请号：US13523589

申请日：2012-06-14

申请人： Brian R. Prasky ,  Chung-Lung K. Shum

发明人： Brian R. Prasky ,  Chung-Lung K. Shum

IPC分类号： G06F12/08

CPC分类号： G06F12/0862 ,  G06F12/0811 ,  G06F12/0897 ,  G06F2212/6024 ,  Y02D10/13

摘要： According to exemplary embodiments, a computer program product, system, and method for prefetching in memory include determining a missed access request for a first line in a first cache level and accessing an entry in a prefetch table, wherein the entry corresponds to a memory block, wherein the entry includes segments of the memory block. Further, the embodiment includes determining a demand segment of the segments in the entry, the demand segment corresponding to a segment of the memory block that includes the first line, reading a first field in the demand segment to determine if a second line in the demand segment is spatially related with respect to accesses of the demand segment and reading a second field in the demand segment to determine if a second segment in the entry is temporally related to the demand segment.

摘要翻译： 根据示例性实施例，用于在存储器中预取的计算机程序产品，系统和方法包括确定第一高速缓存级别中的第一行的错过访问请求并访问预取表中的条目，其中该条目对应于存储器块 ，其中所述条目包括所述存储器块的段。 此外，该实施例包括确定条目中的段的需求段，对应于包括第一行的存储块的段的需求段，读取请求段中的第一字段以确定请求中的第二行 片段与需求片段的访问在空间上相关，并且读取需求片段中的第二字段以确定条目中的第二片段是否在时间上与需求片段相关。

公开(公告)号：US20130246743A1

公开(公告)日：2013-09-19

申请号：US13422589

申请日：2012-03-16

申请人： Mark S. Farrell ,  Charles W. Gainey, JR. ,  Chung-Lung K. Shum ,  Brian Smith

发明人： Mark S. Farrell ,  Charles W. Gainey, JR. ,  Chung-Lung K. Shum ,  Brian Smith

IPC分类号： G06F9/30

CPC分类号： G06F9/30145 ,  G06F9/30021 ,  G06F9/3005 ,  G06F9/30076 ,  G06F9/30101 ,  G06F9/455 ,  G06F11/3636 ,  G06F11/3648

摘要： The invention relates to determining the status of run-time-instrumentation controls. The status is determined by executing a test run-time-instrumentation controls (TRIC) instruction. The TRIC instruction executed in either a supervisor state or a lesser-privileged state. The TRIC instruction determines whether the run-time-instrumentation controls have changed. The run-time-instrumentation controls are set to an initial value using a privileged load run-time-instrumentation controls (LRIC) instruction. The TRIC instruction is fetched and executed. If the TRIC instruction is enabled, then it is determined if the initial value set by the run-time-instrumentation controls has been changed. If the initial value set by the run-time-instrumentation controls has been changed, then a condition code is set to a first value.

摘要翻译： 本发明涉及确定运行时仪表控制的状态。 通过执行测试运行时仪表控制（TRIC）指令来确定状态。 TRIC指令在监督状态或较弱权限状态下执行。 TRIC指令确定运行时仪表控件是否已更改。 使用特权负载运行时仪表控件（LRIC）指令将运行时仪表控件设置为初始值。 获取并执行TRIC指令。 如果启用了TRIC指令，则确定运行时间仪表控制设置的初始值是否已更改。 如果由运行时间检测控件设置的初始值已更改，则将条件代码设置为第一个值。

公开(公告)号：US20130191599A1

公开(公告)日：2013-07-25

申请号：US13354894

申请日：2012-01-20

申请人： Fadi Y. Busaba ,  Steven R. Carlough ,  Christopher A. Krygowski ,  Brian R. Prasky ,  Chung-Lung K. Shum

发明人： Fadi Y. Busaba ,  Steven R. Carlough ,  Christopher A. Krygowski ,  Brian R. Prasky ,  Chung-Lung K. Shum

IPC分类号： G06F12/12

CPC分类号： G06F12/0875 ,  G06F12/126

摘要： A technique is provided for cache management of a cache. The processing circuit determines a miss count and a hit position field during a previous execution of an instruction requesting that a data element be stored in a cache. The miss count and the hit position field are stored for a data element corresponding to an instruction that requests storage of the data element. The processing circuit places the data element in a hierarchical order based on the miss count and/or the hit position field. The hit position field includes a hierarchical position related to the data element in the cache.

摘要翻译： 提供了用于高速缓存的高速缓存管理的技术。 处理电路在先前执行请求数据元素存储在高速缓存中的指令期间确定未命中和命中位置字段。 针对与请求存储数据元素的指令相对应的数据元素存储未命中和命中位置字段。 处理电路基于错过次数和/或命中位置字段将数据元素放置成分层次序。 命中位置字段包括与缓存中的数据元素相关的分层位置。