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    PROCESS IDENTIFIER-BASED CACHE DATA TRANSFER
    2.
    发明申请
    PROCESS IDENTIFIER-BASED CACHE DATA TRANSFER 有权
    基于过程识别器的高速缓存数据传输

    公开(公告)号：US20130332670A1

    公开(公告)日：2013-12-12

    申请号：US13493636

    申请日：2012-06-11

    申请人： Fadi Y. Busaba ,  Steven R. Carlough ,  Christopher A. Krygowski ,  Brian R. Prasky ,  Chung-Lung K. Shum

    发明人： Fadi Y. Busaba ,  Steven R. Carlough ,  Christopher A. Krygowski ,  Brian R. Prasky ,  Chung-Lung K. Shum

    IPC分类号： G06F12/08

    CPC分类号： G06F17/30982 ,  G06F12/0817 ,  G06F12/12

    摘要： Embodiments of the invention relate to process identifier (PID) based cache information transfer. An aspect of the invention includes sending, by a first core of a processor, a PID associated with a cache miss in a first local cache of the first core to a second cache of the processor. Another aspect of the invention includes determining that the PID associated with the cache miss is listed in a PID table of the second cache. Yet another aspect of the invention includes based on the PID being listed in the PID table of the second cache, determining a plurality of entries in a cache directory of the second cache that are associated with the PID. Yet another aspect of the invention includes pushing cache information associated with each of the determined plurality of entries in the cache directory from the second cache to the first local cache.

    摘要翻译： 本发明的实施例涉及基于过程标识符（PID）的高速缓存信息传送。 本发明的一个方面包括由处理器的第一核心将与第一核心的第一本地高速缓存中的高速缓存未命中相关联的PID发送到处理器的第二高速缓存。 本发明的另一方面包括确定与高速缓存未命中相关联的PID被列在第二高速缓存的PID表中。 本发明的另一方面包括基于PID列在第二高速缓存的PID表中，确定与PID相关联的第二高速缓存的高速缓存目录中的多个条目。 本发明的另一方面包括将高速缓存目录中的确定的多个条目中的每一个相关联的缓存信息从第二高速缓存推送到第一本地高速缓存。

    OPERAND FETCHING CONTROL AS A FUNCTION OF BRANCH CONFIDENCE
    4.
    发明申请
    OPERAND FETCHING CONTROL AS A FUNCTION OF BRANCH CONFIDENCE 有权
    操作控制作为分支机构的功能

    公开(公告)号：US20110320774A1

    公开(公告)日：2011-12-29

    申请号：US12822379

    申请日：2010-06-24

    申请人： Christian Jacobi ,  Barry W. Krumm ,  Brian R. Prasky ,  Martin Recktenwald ,  Chung-Lung K. Shum ,  Charles F. Webb ,  Joshua M. Weinberg

    发明人： Christian Jacobi ,  Barry W. Krumm ,  Brian R. Prasky ,  Martin Recktenwald ,  Chung-Lung K. Shum ,  Charles F. Webb ,  Joshua M. Weinberg

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3824 ,  G06F9/30043 ,  G06F9/3806 ,  G06F9/3844 ,  G06F9/3857

    摘要： A system for data operand fetching control includes a computer processor that includes a control unit for determining memory access operations. The control unit is configured to perform a method. The method includes calculating a summation weight value for each instruction in a pipeline, the summation weight value calculated as a function of branch uncertainty and a pendency in which the instruction resides in the pipeline relative to other instructions in the pipeline. The method also includes mapping the summation weight value of a selected instruction that is attempting to access system memory to a memory access control, each memory access control specifying a manner of handling data fetching operations. The method further includes performing a memory access operation for the selected instruction based upon the mapping.

    摘要翻译： 一种用于数据操作数取出控制的系统包括一计算机处理器，该计算机处理器包括用于确定存储器访问操作的控制 控制单元被配置为执行方法。 该方法包括：计算流水线中每个指令的求和权重值，求和作为分支不确定度的函数计算的求和权重值以及相对于流水线中的其他指令，指令驻留在流水线中的挂起。 该方法还包括将尝试访问系统存储器的所选择的指令的求和权重值映射到存储器访问控制，每个存储器访问控制指定处理数据获取操作的方式。 该方法还包括基于映射执行针对所选择的指令的存储器访问操作。

    Cache set replacement order based on temporal set recording
    6.
    发明授权
    Cache set replacement order based on temporal set recording 有权
    基于时间设置记录的缓存集替换顺序

    公开(公告)号：US08806139B2

    公开(公告)日：2014-08-12

    申请号：US13354894

    申请日：2012-01-20

    申请人： Fadi Y. Busaba ,  Steven R. Carlough ,  Christopher A. Krygowski ,  Brian R. Prasky ,  Chung-Lung K. Shum

    发明人： Fadi Y. Busaba ,  Steven R. Carlough ,  Christopher A. Krygowski ,  Brian R. Prasky ,  Chung-Lung K. Shum

    IPC分类号： G06F12/12

    CPC分类号： G06F12/0875 ,  G06F12/126

    摘要： A technique is provided for cache management of a cache. The processing circuit determines a miss count and a hit position field during a previous execution of an instruction requesting that a data element be stored in a cache. The miss count and the hit position field are stored for a data element corresponding to an instruction that requests storage of the data element. The processing circuit places the data element in a hierarchical order based on the miss count and/or the hit position field. The hit position field includes a hierarchical position related to the data element in the cache.

    摘要翻译： 提供了用于高速缓存的高速缓存管理的技术。 处理电路在先前执行请求数据元素存储在高速缓存中的指令期间确定未命中和命中位置字段。 针对与请求存储数据元素的指令相对应的数据元素存储未命中和命中位置字段。 处理电路基于错过次数和/或命中位置字段将数据元素放置成分层次序。 命中位置字段包括与缓存中的数据元素相关的分层位置。

    Reconfigurable recovery modes in high availability processors
    9.
    发明授权
    Reconfigurable recovery modes in high availability processors 有权
    高可用性处理器中可重构的恢复模式

    公开(公告)号：US08954797B2

    公开(公告)日：2015-02-10

    申请号：US13447554

    申请日：2012-04-16

    申请人： Fadi Y. Busaba ,  Steven R. Carlough ,  Christopher A. Krygowski ,  Brian R. Prasky ,  Chung-Lung K. Shum

    发明人： Fadi Y. Busaba ,  Steven R. Carlough ,  Christopher A. Krygowski ,  Brian R. Prasky ,  Chung-Lung K. Shum

    IPC分类号： G06F11/00 ,  G06F11/07

    CPC分类号： G06F11/1446 ,  G06F1/3287 ,  G06F11/0772 ,  G06F11/0781 ,  G06F11/0793 ,  G06F11/1407 ,  G06F11/1425 ,  G06F11/1428 ,  Y02D10/171

    摘要： A computer program product for performing error recovery is configured to perform a method that includes creating, by a processor, a recovery checkpoint. The processor is dynamically switched into a non-recoverable processing mode of operation based on creating the software recovery checkpoint. The non-recoverable processing mode of operation is a mode in which a subset of hardware error recovery resources are powered-down or re-purposed for instruction processing. It is determined, during the non-recoverable processing mode of operation, that a new software recovery checkpoint is required. Based on the determining that a new software recovery checkpoint is required, the processor is dynamically switched into a recoverable processing mode of operation. The recoverable processing mode of operation is a mode in which hardware error recovery resources, including at least one of the hardware error recovery resources in the subset, are purposed for hardware error recovery operations.

    摘要翻译： 用于执行错误恢复的计算机程序产品被配置为执行包括由处理器创建恢复检查点的方法。 基于创建软件恢复检查点，处理器被动态切换到不可恢复的处理操作模式。 不可恢复的处理操作模式是硬件错误恢复资源的子集被掉电或重新用于指令处理的模式。 在不可恢复的处理操作模式下，确定需要新的软件恢复检查点。 基于确定需要新的软件恢复检查点，处理器被动态切换成可恢复的处理操作模式。 可恢复处理操作模式是硬件错误恢复资源（包括该子集中的至少一个硬件错误恢复资源）用于硬件错误恢复操作的模式。

    INSTRUCTION FILTERING
    10.
    发明申请
    INSTRUCTION FILTERING 有权
    指令过滤

    公开(公告)号：US20130339683A1

    公开(公告)日：2013-12-19

    申请号：US13523170

    申请日：2012-06-14

    申请人： James J. Bonanno ,  Adam B. Collura ,  Ulrich Mayer ,  Brian R. Prasky ,  Anthony Saporito ,  Chung-Lung K. Shum

    发明人： James J. Bonanno ,  Adam B. Collura ,  Ulrich Mayer ,  Brian R. Prasky ,  Anthony Saporito ,  Chung-Lung K. Shum

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3844 ,  G06F9/30 ,  G06F9/30047 ,  G06F9/3005 ,  G06F9/3806 ,  G06F9/3836

    摘要： Embodiments relate to instruction filtering. An aspect includes a system for instruction filtering. The system includes memory configured to store instructions accessible by a processor, and the processor includes a tracking array and a tracked instruction logic block. The processor is configured to perform a method including detecting a tracked instruction in an instruction stream, and storing an instruction address of the tracked instruction in the tracking array based on detecting and executing the tracked instruction. The method also includes accessing the tracking array based on an address of instruction data of a subsequently fetched instruction to locate the instruction address of the tracked instruction in the tracking array as an indication of the tracked instruction. Instruction text of the subsequently fetched instruction is marked to indicate previous execution based on the tracking array. An action of the tracked instruction logic block is prevented based on the marked instruction text.

    摘要翻译： 实施例涉及指令过滤。 一个方面包括用于指令过滤的系统。 该系统包括被配置为存储由处理器可访问的指令的存储器，并且处理器包括跟踪阵列和跟踪的指令逻辑块。 处理器被配置为执行包括检测指令流中的跟踪指令并且基于检测和执行跟踪指令将追踪指令的指令地址存储在跟踪数组中的方法。 该方法还包括基于随后获取的指令的指令数据的地址来访问跟踪数组，以将跟踪数组中跟踪的指令的指令地址定位为跟踪指令的指示。 随后获取的指令的指令文本被标记为基于跟踪数组指示先前的执行。 基于标记的指令文本来防止跟踪指令逻辑块的动作。