公开(公告)号：US07087953B2

公开(公告)日：2006-08-08

申请号：US11040862

申请日：2005-01-21

申请人： Peter W. Lee

发明人： Peter W. Lee

IPC分类号： H01L29/788

CPC分类号： H01L27/105 ,  G11C16/0408 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546

摘要： A method for making a unified non-volatile memory (NVM) comprised of a NOR-type flash memory, a NAND-type flash memory, and a 3-transistor EEPROM integrated on the same chip is achieved. This unified NVM can be used in advanced smart card applications. The unification is achieved by forming the array of NVM cells and their peripheral high-voltage NMOS-FETs in a deep triple-P well or P-substrate while making high-voltage PMOS-FETs in a deep N well with breakdown voltages greater than +18 V and greater than −18 V, respectively. This novel NVM structure allows one to have compatible breakdown voltages for programming/erasing (charging and discharging) the floating-gate transistors in the NOR flash, the NAND flash, and 3-transistor EEPROM memory.

摘要翻译： 实现了一种用于制造集成在同一芯片上的NOR型闪速存储器，NAND型闪速存储器和3晶体管EEPROM组成的统一的非易失性存储器（NVM）的方法。 这种统一的NVM可用于高级智能卡应用。 通过在深三阱阱或P衬底中形成NVM单元阵列及其外围高压NMOS-FET，同时在深N阱中制造高电压PMOS-FET，击穿电压大于+ 18 V，大于-18 V。 这种新颖的NVM结构允许具有用于在NOR闪存，NAND闪存和3晶体管EEPROM存储器中的浮动栅极晶体管的编程/擦除（充电和放电）的兼容击穿电压。

公开(公告)号：US07075826B2

公开(公告)日：2006-07-11

申请号：US11036945

申请日：2005-01-14

申请人： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma ,  Koucheng Wu

发明人： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma ,  Koucheng Wu

IPC分类号： G11C16/06

CPC分类号： H01L27/115 ,  G11C11/005 ,  G11C16/0408 ,  G11C16/0416 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3436 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3454 ,  G11C16/3459 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524

摘要： A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+ cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost.

公开(公告)号：US06862223B1

公开(公告)日：2005-03-01

申请号：US10223208

申请日：2002-08-19

申请人： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma ,  Koucheng Wu

发明人： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma ,  Koucheng Wu

IPC分类号： G11C11/34 ,  G11C16/04 ,  H01L27/115

CPC分类号： H01L27/115 ,  G11C11/005 ,  G11C16/0408 ,  G11C16/0416 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3436 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3454 ,  G11C16/3459 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524

摘要： A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost.

摘要翻译： 公开了一种新颖的基于FLASH的EEPROM单元，解码器和布局方案，以消除单元阵列中的面积消耗的划分三阱，并允许字节擦除和字节程序用于高P / E周期。 此外，用于EEPROM部件的处理兼容FLASH单元可以与FLASH和ROM部件集成，从而实现了优异的组合，单片，非易失性存储器。 与所有以前的技术不同，ROM，EEPROM和FLASH本发明的新颖的组合非易失性存储器或任何两个的组合由一个统一的，完全兼容的，高度可扩展的BN +单元和统一过程组成。 此外，其单元操作方案在P / E操作期间具有零阵列开销和零扰动。 该新颖的组合非易失性存储器旨在满足那些需要灵活的写入大小（以字节，页面和块为单位）以低成本的市场的需求。

公开(公告)号：US06777292B2

公开(公告)日：2004-08-17

申请号：US10627183

申请日：2003-07-25

申请人： Peter W. Lee ,  Hsing-Ya Tsao ,  Fu-Chang Hsu ,  Mervyn Wong

发明人： Peter W. Lee ,  Hsing-Ya Tsao ,  Fu-Chang Hsu ,  Mervyn Wong

IPC分类号： H01L21336

CPC分类号： G11C16/3404 ,  G11C16/0416 ,  G11C16/344 ,  H01L27/115 ,  H01L29/66825

摘要： In the present invention a method is shown that uses three concurrent word line voltages in memory cell operations of an a NOR type EEPROM flash memory array. A first concurrent word line voltage controls the operation on a selected word line within a selected memory block. The second concurrent word line voltage inhibits cells on non selected word lines in the selected memory block, and the third concurrent word line voltage inhibits non-selected cells in non-selected blocks from disturb conditions. In addition the three consecutive word line voltages allow a block to be erased, pages within the block to be verified as erased, and pages within the block to be inhibited from further erasure. The three consecutive voltages also allow for the detection of over erasure of cells, correction on a page basis, and verification that the threshold voltage of the corrected cells are above an over erase value but below an erased value. The methods described herein produce a cell threshold voltage that has a narrow voltage distribution.

公开(公告)号：US06757196B1

公开(公告)日：2004-06-29

申请号：US10016898

申请日：2001-12-14

申请人： Hsing-Ya Tsao ,  Peter W. Lee ,  Fu-Chang Hsu

发明人： Hsing-Ya Tsao ,  Peter W. Lee ,  Fu-Chang Hsu

IPC分类号： G11C1604

CPC分类号： G11C16/0433 ,  H01L27/115

摘要： The present invention describes a two transistor flash EEPROM memory cell which has a symmetrical source and drain structure, which permits the cell size not limited by program and erase operations. The memory cell comprises an NMOS floating gate transistor forming a nonvolatile storage device and an NMOS transistor forming an access device. The floating gate transistor is programmed and erased using Fowler-Nordheim channel tunneling. The two transistor memory cell is used in a memory array of columns and rows where a column of cells is coupled by a bit line and a source line, and where a row of cells is coupled by a word line and an access line. The memory array is highly scalable and is targeted for low-voltage, high-speed and high-density programmable logic devices.

摘要翻译： 本发明描述了具有对称的源极和漏极结构的双晶体管快速EEPROM存储单元，这允许单元大小不受编程和擦除操作的限制。 存储单元包括形成非易失性存储器件的NMOS浮栅晶体管和形成存取器件的NMOS晶体管。 使用Fowler-Nordheim通道隧道对浮栅晶体管进行编程和擦除。 两个晶体管存储单元用于列和行的存储器阵列中，其中一列单元由位线和源极线耦合，并且其中一行单元通过字线和存取线耦合。 内存阵列具有高度可扩展性，适用于低电压，高速和高密度可编程逻辑器件。

公开(公告)号：US06628563B1

公开(公告)日：2003-09-30

申请号：US10191228

申请日：2002-07-09

申请人： Fu-Chang Hsu ,  Peter W. Lee ,  Hsing-Ya Tsao

发明人： Fu-Chang Hsu ,  Peter W. Lee ,  Hsing-Ya Tsao

IPC分类号： G11C800

CPC分类号： G11C16/08 ,  G11C2216/22

摘要： A non-volatile integrated circuit memory having an AND-like array structure that is capable of simultaneous reading and writing of digital data to multiple memory cells within the integrated circuit memory has memory cells within an array block of memory cells are arranged in columns and rows. A plurality of block bit lines is in communication with each array block of memory cells such that each block bit line interconnects the memory cells of one column of memory cells within one array block. A plurality of word lines is in communication with each array block of memory cells such that each word line interconnects the memory cells of one row within one array block. The integrated circuit memory further includes a plurality of global bit lines in communication with the array blocks to select a column of the array blocks and to transfer the digital data from and to the array blocks. A bit line selector selectively connects the plurality of global bit lines to the block bit lines. An array controller controls selection of a row of a block of the array, control transfer of the digital data from selected global bit lines to selected block bit lines, control transfer of the digital data to other selected global bit lines from other selected bit lines to allow simultaneous transfer of the digital data from and to selected memory cells.

摘要翻译： 具有AND状阵列结构的非易失性集成电路存储器能够同时读取和写入数字数据到集成电路存储器内的多个存储器单元，存储单元阵列块内的存储单元被排列成列和行 。 多个块位线与存储器单元的每个阵列块通信，使得每个块位线互连一个阵列块内的一列存储器单元的存储单元。 多个字线与存储器单元的每个阵列块通信，使得每个字线互连一个阵列块内的一行的存储单元。 集成电路存储器还包括与阵列块通信的多个全局位线，以选择阵列块的列并将数字数据从阵列块传送到阵列块。 位线选择器有选择地将多个全局位线连接到块位线。 阵列控制器控制对阵列的一行的选择，控制数字数据从所选择的全局位线传送到选择的块位线，控制数字数据从其它所选位线到其它所选择的全局位线的传送 允许从选定的存储器单元同时传送数字数据。

公开(公告)号：US06515910B1

公开(公告)日：2003-02-04

申请号：US10076826

申请日：2002-02-15

申请人： Peter W. Lee ,  Hsing-Ya Tsao ,  Tam Tran ,  Fu-Chang Hsu

发明人： Peter W. Lee ,  Hsing-Ya Tsao ,  Tam Tran ,  Fu-Chang Hsu

IPC分类号： G11C1606

CPC分类号： G11C16/3409 ,  G11C16/3404 ,  G11C16/344 ,  G11C16/3445

摘要： A method to test the erase condition of memory cells in a memory array device is achieved. The method is further extended to methods to detect and correct under erase and over erase conditions. The erase condition of a section of the memory array device is altered to form an erased section and non-erased sections. The control gates of the memory cells in the non-erased sections are forced to a normal off-state voltage sufficient to turn off erased cells. The control gates of the memory cells in non-selected subsections of the erased section are forced to a guaranteed off-state voltage that will turn off erased cells including those that are over erased. The control gates of the memory cells in a selected subsection of the erased section are forced to a check voltage. Thereafter, the bitline current of the selected subsection of the erased section is measured to determine erase condition of the selected subsection of the erase section.

摘要翻译： 实现了对存储器阵列器件中的存储器单元的擦除条件进行测试的方法。 该方法进一步扩展到在擦除和擦除条件下检测和校正的方法。 存储器阵列器件的一部分的擦除条件被改变以形成擦除部分和非擦除部分。 未擦除部分中的存储器单元的控制栅极被迫到足以关闭已擦除单元的正常截止状态电压。 被擦除部分的未选择子部分中的存储器单元的控制栅极被强制为保证的关断状态电压，其将关闭包括那些被擦除的单元的擦除的单元。 被擦除部分的选定子部分中的存储器单元的控制栅极被强制为检查电压。 此后，测量擦除部分的所选子部分的位线电流，以确定擦除部分的所选子部分的擦除条件。

公开(公告)号：US06498752B1

公开(公告)日：2002-12-24

申请号：US09940159

申请日：2001-08-27

申请人： Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Peter W. Lee

发明人： Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Peter W. Lee

IPC分类号： G11C1606

CPC分类号： G11C16/3445 ,  G11C16/16 ,  G11C16/3459

摘要： The present invention discloses a novel method for erasing an ETOX type and an AND type NOR flash memory arrays. The operations of the methods includes block erase which increases the Vt of the memory cell, block erase verify to check if the Vt of the erased cell is greater than a predetermined voltage Vtoff, page reverse program which reduces the Vt of the memory cell below a predetermine voltage Vtmax, reverse program verify which checks that the Vt of the memory cell is below Vtmax, page correction which corrects the Vt of cells on a page basis to be above a predetermined voltage Vtmin, and correction verify which checks that the Vt of the memory cells is above Vtmin. According to the present invention, the erase operation is performed to increase the Vt of erased cells by applying the positive high voltages to the selected word lines with bit lines and source lines grounded. The reverse program operation is performed to decrease the Vt of erased cells by applying the negative high voltage to the selected word lines with the source lines and bit lines grounded. For the ETOX cell an FN tunneling scheme is utilized for the Erase operation and CHE for the correction operation. The AND cell uses FN tunneling for both erase and correction operations.

摘要翻译： 本发明公开了一种用于擦除ETOX型和AND型NOR闪存阵列的新方法。 方法的操作包括增加存储器单元的Vt的块擦除，块擦除验证以检查擦除单元的Vt是否大于预定电压Vtoff，页面反向程序，其将存储器单元的Vt减小到低于 预先确定电压Vtmax，反向程序验证哪个检查存储器单元的Vt低于Vtmax，将页面上的单元格的Vt校正为高于预定电压Vtmin的页面校正，以及校正验证哪个检查Vt 存储单元高于Vtmin。 根据本发明，执行擦除操作以通过将位线和源极线接地的正高电压施加到所选择的字线来增加擦除单元的Vt。 执行反向编程操作以通过将源极线和位线接地来对所选择的字线施加负高电压来减小擦除单元的Vt。 对于ETOX单元，使用FN隧道方案进行擦除操作和CHE进行校正操作。 AND单元使用FN隧道进行擦除和校正操作。

公开(公告)号：US06275417B1

公开(公告)日：2001-08-14

申请号：US09680651

申请日：2000-10-06

申请人： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao

发明人： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao

IPC分类号： G11C1604

CPC分类号： G11C11/5642 ,  G11C7/06 ,  G11C11/5621 ,  G11C16/26 ,  G11C2211/5634

摘要： Data stored in multi-level memory cells is rapidly read out with high resolution by generating and coupling a predetermined and preferably low number of large magnitude jump-like voltage changes to the control gates of the memory cells. The magnitude of the jumps can be a substantial fraction of the power supply level and will be many times the &Dgr;Vt levels associated with the memory cells, e.g., the control gate voltage changes in jump-steps from say 4 V to 6 V to 8 V. Use of a low number of jump-steps (e.g., two or three) reduces read out time by permitting read out of a plurality of Vt levels during a given control voltage magnitude. Further, use of large but different magnitude control gate voltages provides good read out resolution over the range of Vt values. Reference cells are provided to improve tracking, and DRAM-type sense amplifiers are provided to maintain high noise immunity.

摘要翻译： 存储在多电平存储单元中的数据通过产生并将预定的和优选的低数量的大幅度的类似跳变的电压变化耦合到存储器单元的控制栅极而以高分辨率快速读出。 跳跃的幅度可以是电源电平的很大一部分，并且将是与存储器单元相关联的DELTAVt电平的许多倍，例如，控制栅极电压在从4V变为6V至8V的跳变步长 使用低数量的跳跃步骤（例如，两个或三个）通过允许在给定的控制电压幅度期间读出多个Vt电平来减少读出时间。 此外，使用大但不同幅度的栅极电压在Vt值的范围内提供良好的读出分辨率。 提供参考单元以改善跟踪，并且提供DRAM型读出放大器以保持高抗噪声性。

公开(公告)号：US06258668B1

公开(公告)日：2001-07-10

申请号：US09487501

申请日：2000-01-19

申请人： Peter W. Lee ,  Hung-Sheng Chen ,  Vei-Han Chan

发明人： Peter W. Lee ,  Hung-Sheng Chen ,  Vei-Han Chan

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  G11C16/0425 ,  G11C16/0491 ,  H01L27/115

摘要： In this invention a process for a flash memory cell and an architecture for using the flash memory cell is disclosed to provide a nonvolatile memory having a high storage density. Adjacent columns of cells share the same source and the source line connecting these sources runs vertically in the memory layout, connecting to the sources of adjacent columns memory cells. Bit lines connect to drains of cells in adjacent columns and are laid out vertically, alternating with source lines in an every other column scheme. Wordlines made of a second layer of polysilicon form control gates of the flash memory cells and are continuous over the full width of a memory partition. Programming is done in a vertical page using hot electrons to inject charge onto the floating gates. the cells are erased using Fowler-Nordheim tunneling of electrons from the floating gate to the control gate by way of inter polysilicon oxide formed on the walls of the floating gates.

摘要翻译： 在本发明中，公开了一种用于闪存单元的方法和用于使用闪存单元的架构，以提供具有高存储密度的非易失性存储器。 单元格的相邻列共享相同的源，并且连接这些源的源行在存储器布局中垂直运行，连接到相邻列存储单元的源。 位线连接到相邻列中的单元格的漏极，并且在每个其他列方案中垂直布置，与源极线交替。 由第二层多晶硅制成的字线形成闪存单元的控制栅极，并且在存储器分区的整个宽度上是连续的。 使用热电子在垂直页面中进行编程，以将电荷注入到浮动栅极上。 通过使用Fowler-Nordheim从浮置栅极到控制栅极的隧道，通过在浮栅的壁上形成的多晶硅氧化物来消除电池。